mirror of
https://github.com/skyline-emu/skyline.git
synced 2024-12-22 22:11:49 +01:00
Hookup various DMA engine features
The DMA engine now supports these additional functions: pitch (to pitch) copies, subrect copies, split copies.
This commit is contained in:
TheASVigilante
Billy Laws
parent
fd205ff0a9
commit
4c3fed6cd0
@ -8,26 +8,18 @@
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#include "maxwell_dma.h"
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namespace skyline::gpu::interconnect {
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using IOVA = soc::gm20b::IOVA;
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MaxwellDma::MaxwellDma(GPU &gpu, soc::gm20b::ChannelContext &channelCtx)
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: gpu{gpu},
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channelCtx{channelCtx},
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executor{channelCtx.executor} {}
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void MaxwellDma::Copy(IOVA dst, IOVA src, size_t size) {
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(src, size)};
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(dst, size)};
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if (srcMappings.size() > 1 || dstMappings.size() > 1)
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Logger::Warn("Split mapping are unsupported for DMA copies");
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auto srcBuf{gpu.buffer.FindOrCreate(srcMappings.front(), executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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void MaxwellDma::Copy(span<u8> dstMapping, span<u8> srcMapping) {
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auto srcBuf{gpu.buffer.FindOrCreate(srcMapping, executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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executor.AttachLockedBuffer(buffer, std::move(lock));
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})};
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ContextLock srcBufLock{executor.tag, srcBuf};
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auto dstBuf{gpu.buffer.FindOrCreate(dstMappings.front(), executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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auto dstBuf{gpu.buffer.FindOrCreate(dstMapping, executor.tag, [this](std::shared_ptr<Buffer> buffer, ContextLock<Buffer> &&lock) {
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executor.AttachLockedBuffer(buffer, std::move(lock));
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})};
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ContextLock dstBufLock{executor.tag, dstBuf};
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@ -22,8 +22,6 @@ namespace skyline::gpu::interconnect {
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*/
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class MaxwellDma {
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private:
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using IOVA = soc::gm20b::IOVA;
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GPU &gpu;
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soc::gm20b::ChannelContext &channelCtx;
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gpu::interconnect::CommandExecutor &executor;
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@ -31,6 +29,6 @@ namespace skyline::gpu::interconnect {
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public:
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MaxwellDma(GPU &gpu, soc::gm20b::ChannelContext &channelCtx);
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void Copy(IOVA dst, IOVA src, size_t size);
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void Copy(span<u8> dstMapping, span<u8> srcMapping);
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};
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}
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@ -14,7 +14,8 @@ namespace skyline::soc::gm20b::engine {
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MaxwellDma::MaxwellDma(const DeviceState &state, ChannelContext &channelCtx)
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: channelCtx{channelCtx},
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syncpoints{state.soc->host1x.syncpoints},
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interconnect{*state.gpu, channelCtx} {}
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interconnect{*state.gpu, channelCtx},
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copyCache(0) {}
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__attribute__((always_inline)) void MaxwellDma::CallMethod(u32 method, u32 argument) {
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Logger::Verbose("Called method in Maxwell DMA: 0x{:X} args: 0x{:X}", method, argument);
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@ -30,51 +31,225 @@ namespace skyline::soc::gm20b::engine {
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}
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void MaxwellDma::LaunchDma() {
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if (*registers.lineLengthIn == 0)
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return; // Nothing to copy
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if (registers.launchDma->remapEnable) {
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Logger::Warn("DMA remapping is unimplemented!");
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return;
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}
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if (registers.launchDma->multiLineEnable) {
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channelCtx.executor.Submit();
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if (registers.launchDma->srcMemoryLayout == Registers::LaunchDma::MemoryLayout::Pitch &&
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registers.launchDma->dstMemoryLayout == Registers::LaunchDma::MemoryLayout::BlockLinear)
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CopyPitchToBlockLinear();
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else if (registers.launchDma->srcMemoryLayout == Registers::LaunchDma::MemoryLayout::BlockLinear &&
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registers.launchDma->dstMemoryLayout == Registers::LaunchDma::MemoryLayout::Pitch)
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CopyBlockLinearToPitch();
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else
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Logger::Warn("Unimplemented multi-line copy type: {} -> {}!",
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static_cast<u8>(registers.launchDma->srcMemoryLayout), static_cast<u8>(registers.launchDma->dstMemoryLayout));
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} else {
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// 1D buffer copy
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// TODO: implement swizzled 1D copies based on VMM 'kind'
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Logger::Debug("src: 0x{:X} dst: 0x{:X} size: 0x{:X}", u64{*registers.offsetIn}, u64{*registers.offsetOut}, *registers.lineLengthIn);
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interconnect.Copy(u64{*registers.offsetOut}, u64{*registers.offsetIn}, u64{*registers.lineLengthIn});
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}
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DmaCopy();
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ReleaseSemaphore();
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}
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void MaxwellDma::DmaCopy() {
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if (registers.launchDma->multiLineEnable) {
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if (registers.launchDma->remapEnable) [[unlikely]] {
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Logger::Warn("Remapped DMA copies are unimplemented!");
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return;
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}
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channelCtx.executor.Submit();
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if (registers.launchDma->srcMemoryLayout == registers.launchDma->dstMemoryLayout) [[unlikely]] {
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// Pitch to Pitch copy
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if (registers.launchDma->srcMemoryLayout == Registers::LaunchDma::MemoryLayout::Pitch) [[likely]] {
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetIn, *registers.pitchIn * *registers.lineCount)};
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetOut, *registers.pitchOut * *registers.lineCount)};
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if (srcMappings.size() != 1 || dstMappings.size() != 1) [[unlikely]] {
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HandleCopy(srcMappings, dstMappings, *registers.lineLengthIn, *registers.lineLengthIn, [&](u8 *src, u8 *dst) {
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// Both Linear, copy as is.
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if ((*registers.pitchIn == *registers.pitchOut) && (*registers.pitchIn == *registers.lineLengthIn))
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std::memcpy(dst, src, *registers.lineLengthIn * *registers.lineCount);
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else
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for (u32 linesToCopy{*registers.lineCount}, srcCopyOffset{}, dstCopyOffset{}; linesToCopy; --linesToCopy, srcCopyOffset += *registers.pitchIn, dstCopyOffset += *registers.pitchOut)
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std::memcpy(dst + dstCopyOffset, src + srcCopyOffset, *registers.lineLengthIn);
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});
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} else [[likely]] {
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// Both Linear, copy as is.
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if ((*registers.pitchIn == *registers.pitchOut) && (*registers.pitchIn == *registers.lineLengthIn))
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interconnect.Copy(dstMappings.front(), srcMappings.front());
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else
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for (u32 linesToCopy{*registers.lineCount}, srcCopyOffset{}, dstCopyOffset{}; linesToCopy; --linesToCopy, srcCopyOffset += *registers.pitchIn, dstCopyOffset += *registers.pitchOut)
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interconnect.Copy(dstMappings.front().subspan(dstCopyOffset, u64{*registers.lineLengthIn}), srcMappings.front().subspan(srcCopyOffset, u64{*registers.lineLengthIn}));
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}
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} else {
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Logger::Warn("BlockLinear to BlockLinear DMA copies are unimplemented!");
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}
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return;
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} else if (registers.launchDma->srcMemoryLayout == Registers::LaunchDma::MemoryLayout::BlockLinear) {
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CopyBlockLinearToPitch();
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} else [[likely]] {
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CopyPitchToBlockLinear();
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}
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} else {
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// 1D copy
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// TODO: implement swizzled 1D copies based on VMM 'kind'
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Logger::Debug("src: 0x{:X} dst: 0x{:X} size: 0x{:X}", u64{*registers.offsetIn}, u64{*registers.offsetOut}, *registers.lineLengthIn);
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size_t dstBpp{registers.launchDma->remapEnable ? static_cast<size_t>(registers.remapComponents->NumDstComponents() * registers.remapComponents->ComponentSize()) : 1};
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetIn, *registers.lineLengthIn)};
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetOut, *registers.lineLengthIn * dstBpp)};
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if (registers.launchDma->remapEnable) [[unlikely]] {
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Logger::Warn("Remapped DMA copies are unimplemented!");
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} else {
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if (srcMappings.size() != 1 || dstMappings.size() != 1) [[unlikely]]
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channelCtx.asCtx->gmmu.Copy(u64{*registers.offsetOut}, u64{*registers.offsetIn}, *registers.lineLengthIn);
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else
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interconnect.Copy(dstMappings.front(), srcMappings.front());
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}
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}
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}
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void MaxwellDma::HandleCopy(TranslatedAddressRange srcMappings, TranslatedAddressRange dstMappings, size_t srcSize, size_t dstSize, auto copyCallback) {
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bool isSrcSplit{};
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u8 *src{srcMappings.front().data()}, *dst{dstMappings.front().data()};
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if (srcMappings.size() != 1) {
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if (copyCache.size() < srcSize)
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copyCache.resize(srcSize);
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src = copyCache.data();
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channelCtx.asCtx->gmmu.Read(src, u64{*registers.offsetIn}, srcSize);
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isSrcSplit = true;
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}
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if (dstMappings.size() != 1) {
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// If both the source and destination are split
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if (isSrcSplit) {
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if (copyCache.size() < (srcSize + dstSize))
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copyCache.resize(srcSize + dstSize);
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dst = copyCache.data() + srcSize;
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} else {
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if (copyCache.size() < dstSize)
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copyCache.resize(dstSize);
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dst = copyCache.data();
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}
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// If the destination is not entirely filled by the copy we copy it's current state in the cache to prevent clearing of other data.
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if (registers.launchDma->dstMemoryLayout == Registers::LaunchDma::MemoryLayout::BlockLinear)
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channelCtx.asCtx->gmmu.Read(dst, u64{*registers.offsetOut}, dstSize);
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}
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copyCallback(src, dst);
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if (dstMappings.size() != 1)
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channelCtx.asCtx->gmmu.Write(u64{*registers.offsetOut}, dst, dstSize);
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// If the cache is over 5 MBs large then we clamp it to not waste memory
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if (copyCache.size() > 5242880) [[unlikely]]
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copyCache.resize(5242880);
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}
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void MaxwellDma::CopyBlockLinearToPitch() {
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if (registers.srcSurface->blockSize.Width() != 1) [[unlikely]] {
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Logger::Error("Blocklinear surfaces with a non-one block width are unsupported on the Tegra X1: {}", registers.srcSurface->blockSize.Width());
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return;
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}
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gpu::texture::Dimensions srcDimensions{registers.srcSurface->width, registers.srcSurface->height, registers.srcSurface->depth};
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size_t srcLayerStride{gpu::texture::GetBlockLinearLayerSize(srcDimensions, 1, 1, 1, registers.srcSurface->blockSize.Height(), registers.srcSurface->blockSize.Depth())};
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size_t srcLayerAddress{*registers.offsetIn + (registers.srcSurface->layer * srcLayerStride)};
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// Get source address
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetIn, srcLayerStride)};
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gpu::texture::Dimensions dstDimensions{*registers.lineLengthIn, *registers.lineCount, registers.srcSurface->depth};
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size_t dstSize{*registers.pitchOut * dstDimensions.height * dstDimensions.depth}; // If remapping is not enabled there are only 1 bytes per pixel
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// Get destination address
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetOut, dstSize)};
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auto copyFunc{[&](u8 *src, u8 *dst) {
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if ((util::AlignDown(srcDimensions.width, 64) != util::AlignDown(dstDimensions.width, 64))
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|| registers.srcSurface->origin.x || registers.srcSurface->origin.y) {
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gpu::texture::CopyBlockLinearToPitchSubrect(
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dstDimensions, srcDimensions,
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1, 1, 1, *registers.pitchOut,
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registers.srcSurface->blockSize.Height(), registers.srcSurface->blockSize.Depth(),
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src, dst,
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registers.srcSurface->origin.x, registers.srcSurface->origin.y
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);
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} else [[likely]] {
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gpu::texture::CopyBlockLinearToPitch(
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dstDimensions,
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1, 1, 1, *registers.pitchOut,
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registers.srcSurface->blockSize.Height(), registers.srcSurface->blockSize.Depth(),
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src, dst
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);
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}
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}};
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Logger::Debug("{}x{}x{}@0x{:X} -> {}x{}x{}@0x{:X}", srcDimensions.width, srcDimensions.height, srcDimensions.depth, srcLayerAddress, dstDimensions.width, dstDimensions.height, dstDimensions.depth, u64{*registers.offsetOut});
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if (srcMappings.size() != 1 || dstMappings.size() != 1) [[unlikely]]
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HandleCopy(srcMappings, dstMappings, srcLayerStride, dstSize, copyFunc);
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else [[likely]]
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copyFunc(srcMappings.front().data(), dstMappings.front().data());
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}
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void MaxwellDma::CopyPitchToBlockLinear() {
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if (registers.dstSurface->blockSize.Width() != 1) [[unlikely]] {
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Logger::Error("Blocklinear surfaces with a non-one block width are unsupported on the Tegra X1: {}", registers.srcSurface->blockSize.Width());
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return;
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}
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gpu::texture::Dimensions srcDimensions{*registers.lineLengthIn, *registers.lineCount, registers.dstSurface->depth};
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size_t srcSize{*registers.pitchIn * srcDimensions.height * srcDimensions.depth}; // If remapping is not enabled there are only 1 bytes per pixel
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// Get source address
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetIn, srcSize)};
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gpu::texture::Dimensions dstDimensions{registers.dstSurface->width, registers.dstSurface->height, registers.dstSurface->depth};
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size_t dstLayerStride{gpu::texture::GetBlockLinearLayerSize(dstDimensions, 1, 1, 1, registers.dstSurface->blockSize.Height(), registers.dstSurface->blockSize.Depth())};
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size_t dstLayerAddress{*registers.offsetOut + (registers.dstSurface->layer * dstLayerStride)};
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// Get destination address
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetOut, dstLayerStride)};
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Logger::Debug("{}x{}x{}@0x{:X} -> {}x{}x{}@0x{:X}", srcDimensions.width, srcDimensions.height, srcDimensions.depth, u64{*registers.offsetIn}, dstDimensions.width, dstDimensions.height, dstDimensions.depth, dstLayerAddress);
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auto copyFunc{[&](u8 *src, u8 *dst) {
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if ((util::AlignDown(srcDimensions.width, 64) != util::AlignDown(dstDimensions.width, 64))
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|| registers.dstSurface->origin.x || registers.dstSurface->origin.y) {
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gpu::texture::CopyPitchToBlockLinearSubrect(
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srcDimensions, dstDimensions,
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1, 1, 1, *registers.pitchIn,
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registers.dstSurface->blockSize.Height(), registers.dstSurface->blockSize.Depth(),
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src, dst,
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registers.dstSurface->origin.x, registers.dstSurface->origin.y
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);
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} else [[likely]] {
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gpu::texture::CopyPitchToBlockLinear(
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srcDimensions,
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1, 1, 1, *registers.pitchIn,
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registers.dstSurface->blockSize.Height(), registers.dstSurface->blockSize.Depth(),
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src, dst
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);
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}
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}};
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if (srcMappings.size() != 1 || dstMappings.size() != 1) [[unlikely]]
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HandleCopy(srcMappings, dstMappings, srcSize, dstLayerStride, copyFunc);
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else [[likely]]
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copyFunc(srcMappings.front().data(), dstMappings.front().data());
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}
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void MaxwellDma::ReleaseSemaphore() {
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if (registers.launchDma->reductionEnable)
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if (registers.launchDma->reductionEnable) [[unlikely]]
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Logger::Warn("Semaphore reduction is unimplemented!");
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u64 address{registers.semaphore->address};
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u64 payload{registers.semaphore->payload};
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switch (registers.launchDma->semaphoreType) {
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case Registers::LaunchDma::SemaphoreType::ReleaseOneWordSemaphore:
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channelCtx.asCtx->gmmu.Write(address, registers.semaphore->payload);
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channelCtx.asCtx->gmmu.Write(address, payload);
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Logger::Debug("address: 0x{:X} payload: {}", address, payload);
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break;
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case Registers::LaunchDma::SemaphoreType::ReleaseFourWordSemaphore: {
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// Write timestamp first to ensure correct ordering
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u64 timestamp{GetGpuTimeTicks()};
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channelCtx.asCtx->gmmu.Write(address + 8, timestamp);
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channelCtx.asCtx->gmmu.Write(address, static_cast<u64>(payload));
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channelCtx.asCtx->gmmu.Write(address, payload);
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Logger::Debug("address: 0x{:X} payload: {} timestamp: {}", address, payload, timestamp);
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break;
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}
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@ -83,116 +258,6 @@ namespace skyline::soc::gm20b::engine {
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}
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}
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void MaxwellDma::CopyPitchToBlockLinear() {
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if (registers.dstSurface->blockSize.Depth() > 1 || registers.dstSurface->depth > 1) {
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Logger::Warn("3D DMA engine copies are unimplemented");
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return;
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}
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if (registers.dstSurface->blockSize.Width() != 1) {
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Logger::Warn("DMA engine copies with block widths other than 1 are unimplemented");
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return;
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}
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u32 bytesPerPixel{static_cast<u32>(registers.remapComponents->ComponentSize() * registers.remapComponents->NumSrcComponents())};
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if (bytesPerPixel * *registers.lineLengthIn != *registers.pitchIn) {
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Logger::Warn("Non-linear DMA source textures are not implemented");
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return;
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}
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if (registers.dstSurface->origin.x || registers.dstSurface->origin.y) {
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Logger::Warn("Non-zero origin DMA copies are not implemented");
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return;
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}
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if (*registers.lineLengthIn != registers.dstSurface->width)
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Logger::Warn("DMA copy width mismatch: src: {} dst: {}", *registers.lineLengthIn, registers.dstSurface->width);
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gpu::texture::Dimensions srcDimensions{*registers.lineLengthIn, *registers.lineCount, 1};
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size_t srcStride{srcDimensions.width * srcDimensions.height * bytesPerPixel};
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auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetIn, srcStride)};
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if (srcMappings.size() != 1) {
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Logger::Warn("DMA for split textures is unimplemented");
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return;
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}
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gpu::texture::Dimensions dstDimensions{registers.dstSurface->width, registers.dstSurface->height, registers.dstSurface->depth};
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dstDimensions.width = *registers.lineLengthIn; // We do not support copying subrects so we need the width to match on the source and destination
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size_t dstBlockHeight{registers.dstSurface->blockSize.Height()}, dstBlockDepth{registers.dstSurface->blockSize.Depth()};
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size_t dstLayerStride{gpu::texture::GetBlockLinearLayerSize(dstDimensions, 1, 1, bytesPerPixel, dstBlockHeight, dstBlockDepth)};
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size_t dstLayerAddress{*registers.offsetOut + (registers.dstSurface->layer * dstLayerStride)};
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auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(dstLayerAddress, dstLayerStride)};
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if (dstMappings.size() != 1) {
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Logger::Warn("DMA for split textures is unimplemented");
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return;
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}
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Logger::Debug("{}x{}@0x{:X} -> {}x{}@0x{:X}", srcDimensions.width, srcDimensions.height, u64{*registers.offsetIn}, dstDimensions.width, dstDimensions.height, dstLayerAddress);
|
||||
|
||||
gpu::texture::CopyLinearToBlockLinear(
|
||||
dstDimensions,
|
||||
1, 1, bytesPerPixel,
|
||||
dstBlockHeight, dstBlockDepth,
|
||||
srcMappings.front().data(), dstMappings.front().data()
|
||||
);
|
||||
}
|
||||
|
||||
void MaxwellDma::CopyBlockLinearToPitch() {
|
||||
if (registers.srcSurface->blockSize.Depth() > 1 || registers.srcSurface->depth > 1) {
|
||||
Logger::Warn("3D DMA engine copies are unimplemented");
|
||||
return;
|
||||
}
|
||||
|
||||
if (registers.srcSurface->blockSize.Width() != 1) {
|
||||
Logger::Warn("DMA engine copies with block widths other than 1 are unimplemented");
|
||||
return;
|
||||
}
|
||||
|
||||
u32 bytesPerPixel{static_cast<u32>(registers.remapComponents->ComponentSize() * registers.remapComponents->NumSrcComponents())};
|
||||
if (bytesPerPixel * *registers.lineLengthIn != *registers.pitchOut) {
|
||||
Logger::Warn("Non-linear DMA destination textures are not implemented");
|
||||
return;
|
||||
}
|
||||
|
||||
if (registers.srcSurface->origin.x || registers.srcSurface->origin.y) {
|
||||
Logger::Warn("Non-zero origin DMA copies are not implemented");
|
||||
return;
|
||||
}
|
||||
|
||||
if (*registers.lineLengthIn != registers.srcSurface->width)
|
||||
Logger::Warn("DMA copy width mismatch: src: {} dst: {}", *registers.lineLengthIn, registers.dstSurface->width);
|
||||
|
||||
gpu::texture::Dimensions srcDimensions{registers.srcSurface->width, registers.srcSurface->height, registers.srcSurface->depth};
|
||||
srcDimensions.width = *registers.lineLengthIn; // We do not support copying subrects so we need the width to match on the source and destination
|
||||
size_t srcBlockHeight{registers.srcSurface->blockSize.Height()}, srcBlockDepth{registers.srcSurface->blockSize.Depth()};
|
||||
size_t srcStride{gpu::texture::GetBlockLinearLayerSize(srcDimensions, 1, 1, bytesPerPixel, srcBlockHeight, srcBlockDepth)};
|
||||
|
||||
auto srcMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetIn, srcStride)};
|
||||
if (srcMappings.size() != 1) {
|
||||
Logger::Warn("DMA for split textures is unimplemented");
|
||||
return;
|
||||
}
|
||||
|
||||
gpu::texture::Dimensions dstDimensions{*registers.lineLengthIn, *registers.lineCount, 1};
|
||||
size_t dstStride{dstDimensions.width * dstDimensions.height * bytesPerPixel};
|
||||
|
||||
auto dstMappings{channelCtx.asCtx->gmmu.TranslateRange(*registers.offsetOut, dstStride)};
|
||||
if (dstMappings.size() != 1) {
|
||||
Logger::Warn("DMA for split textures is unimplemented");
|
||||
return;
|
||||
}
|
||||
|
||||
Logger::Debug("{}x{}@0x{:X} -> {}x{}@0x{:X}", srcDimensions.width, srcDimensions.height, u64{*registers.offsetIn}, dstDimensions.width, dstDimensions.height, u64{*registers.offsetOut});
|
||||
|
||||
gpu::texture::CopyBlockLinearToLinear(
|
||||
srcDimensions,
|
||||
1, 1, bytesPerPixel,
|
||||
srcBlockHeight, srcBlockDepth,
|
||||
srcMappings.front().data(), dstMappings.front().data());
|
||||
}
|
||||
|
||||
void MaxwellDma::CallMethodBatchNonInc(u32 method, span<u32> arguments) {
|
||||
for (u32 argument : arguments)
|
||||
HandleMethod(method, argument);
|
||||
|
||||
@ -23,17 +23,22 @@ namespace skyline::soc::gm20b::engine {
|
||||
host1x::SyncpointSet &syncpoints;
|
||||
ChannelContext &channelCtx;
|
||||
gpu::interconnect::MaxwellDma interconnect;
|
||||
std::vector<u8> copyCache;
|
||||
|
||||
void HandleMethod(u32 method, u32 argument);
|
||||
|
||||
void DmaCopy();
|
||||
|
||||
void HandleCopy(TranslatedAddressRange srcMappings, TranslatedAddressRange dstMappings, size_t srcSize, size_t dstSize, auto copyCallback);
|
||||
|
||||
void CopyBlockLinearToPitch();
|
||||
|
||||
void CopyPitchToBlockLinear();
|
||||
|
||||
void LaunchDma();
|
||||
|
||||
void ReleaseSemaphore();
|
||||
|
||||
void CopyPitchToBlockLinear();
|
||||
|
||||
void CopyBlockLinearToPitch();
|
||||
|
||||
public:
|
||||
/**
|
||||
* @url https://github.com/NVIDIA/open-gpu-doc/blob/master/classes/dma-copy/clb0b5.h
|
||||
|
||||
Loading…
Reference in New Issue
Block a user