Reformat maxwell3d interconnect codebase

This commit is contained in:
Billy Laws 2022-10-09 13:57:47 +01:00
parent 3766be59e7
commit 62a165b51e
10 changed files with 153 additions and 133 deletions

View File

@ -15,7 +15,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
}; };
private: private:
dirty::BoundSubresource<EngineRegisters> engine; dirty::BoundSubresource <EngineRegisters> engine;
public: public:
ConstantBufferSelectorState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine); ConstantBufferSelectorState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine);
@ -32,7 +32,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
struct ConstantBuffer { struct ConstantBuffer {
BufferView view; BufferView view;
void Read(CommandExecutor &executor, span<u8> dstBuffer, size_t srcOffset); void Read(CommandExecutor &executor, span <u8> dstBuffer, size_t srcOffset);
template<typename T> template<typename T>
T Read(CommandExecutor &executor, size_t srcOffset) { T Read(CommandExecutor &executor, size_t srcOffset) {
@ -49,7 +49,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
*/ */
class ConstantBuffers { class ConstantBuffers {
private: private:
dirty::ManualDirtyState<ConstantBufferSelectorState> selectorState; dirty::ManualDirtyState <ConstantBufferSelectorState> selectorState;
public: public:
ConstantBufferSet boundConstantBuffers; ConstantBufferSet boundConstantBuffers;
@ -68,7 +68,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
void MarkAllDirty(); void MarkAllDirty();
void Load(InterconnectContext &ctx, span<u32> data, u32 offset); void Load(InterconnectContext &ctx, span <u32> data, u32 offset);
void Bind(InterconnectContext &ctx, engine::ShaderStage stage, size_t index); void Bind(InterconnectContext &ctx, engine::ShaderStage stage, size_t index);

View File

@ -174,8 +174,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
ctx.gpu.shader.ResetPools(); ctx.gpu.shader.ResetPools();
using PipelineStage = engine::Pipeline::Shader::Type; using PipelineStage = engine::Pipeline::Shader::Type;
auto pipelineStage{[](size_t i){ return static_cast<PipelineStage>(i); }}; auto pipelineStage{[](size_t i) { return static_cast<PipelineStage>(i); }};
auto stageIdx{[](PipelineStage stage){ return static_cast<u8>(stage); }}; auto stageIdx{[](PipelineStage stage) { return static_cast<u8>(stage); }};
std::array<Shader::IR::Program, engine::PipelineCount> programs; std::array<Shader::IR::Program, engine::PipelineCount> programs;
bool ignoreVertexCullBeforeFetch{}; bool ignoreVertexCullBeforeFetch{};
@ -435,9 +435,11 @@ namespace skyline::gpu::interconnect::maxwell3d {
}); });
if (binding.GetInputRate() == vk::VertexInputRate::eInstance) { if (binding.GetInputRate() == vk::VertexInputRate::eInstance) {
if (!ctx.gpu.traits.supportsVertexAttributeDivisor) [[unlikely]] if (!ctx.gpu.traits.supportsVertexAttributeDivisor)
[[unlikely]]
Logger::Warn("Vertex attribute divisor used on guest without host support"); Logger::Warn("Vertex attribute divisor used on guest without host support");
else if (!ctx.gpu.traits.supportsVertexAttributeZeroDivisor && binding.divisor == 0) [[unlikely]] else if (!ctx.gpu.traits.supportsVertexAttributeZeroDivisor && binding.divisor == 0)
[[unlikely]]
Logger::Warn("Vertex attribute zero divisor used on guest without host support"); Logger::Warn("Vertex attribute zero divisor used on guest without host support");
else else
bindingDivisorDescs.push_back({ bindingDivisorDescs.push_back({
@ -668,7 +670,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
size_t primaryCbufOffset{desc.cbuf_offset + elemOffset}; size_t primaryCbufOffset{desc.cbuf_offset + elemOffset};
u32 primaryVal{primaryCbuf.Read<u32>(ctx.executor, primaryCbufOffset)}; u32 primaryVal{primaryCbuf.Read<u32>(ctx.executor, primaryCbufOffset)};
if constexpr (requires { desc.has_secondary; } ) { if constexpr (requires { desc.has_secondary; }) {
if (desc.has_secondary) { if (desc.has_secondary) {
ConstantBuffer &secondaryCbuf{constantBuffers[desc.secondary_cbuf_index]}; ConstantBuffer &secondaryCbuf{constantBuffers[desc.secondary_cbuf_index]};
size_t secondaryCbufOffset{desc.secondary_cbuf_offset + elemOffset}; size_t secondaryCbufOffset{desc.secondary_cbuf_offset + elemOffset};
@ -677,7 +679,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
} }
} }
return { .raw = primaryVal }; return {.raw = primaryVal};
} }
static vk::DescriptorImageInfo GetTextureBinding(InterconnectContext &ctx, const Shader::TextureDescriptor &desc, Samplers &samplers, Textures &textures, BindlessHandle handle) { static vk::DescriptorImageInfo GetTextureBinding(InterconnectContext &ctx, const Shader::TextureDescriptor &desc, Samplers &samplers, Textures &textures, BindlessHandle handle) {

View File

@ -207,5 +207,4 @@ namespace skyline::gpu::interconnect::maxwell3d {
return sampler.get(); return sampler.get();
} }
} }

View File

@ -39,7 +39,6 @@ namespace skyline::gpu::interconnect::maxwell3d {
tsl::robin_map<TextureSamplerControl, std::unique_ptr<vk::raii::Sampler>, util::ObjectHash<TextureSamplerControl>> texSamplerStore; tsl::robin_map<TextureSamplerControl, std::unique_ptr<vk::raii::Sampler>, util::ObjectHash<TextureSamplerControl>> texSamplerStore;
std::vector<vk::raii::Sampler *> texSamplerCache; std::vector<vk::raii::Sampler *> texSamplerCache;
public: public:
Samplers(DirtyManager &manager, const SamplerPoolState::EngineRegisters &engine); Samplers(DirtyManager &manager, const SamplerPoolState::EngineRegisters &engine);

View File

@ -184,7 +184,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
}; };
using SetBaseStencilStateCmd = CmdHolder<SetBaseStencilStateCmdImpl>; using SetBaseStencilStateCmd = CmdHolder<SetBaseStencilStateCmdImpl>;
struct SetDescriptorSetWithUpdateCmdImpl { template<bool PushDescriptor>
struct SetDescriptorSetCmdImpl {
void Record(GPU &gpu, vk::raii::CommandBuffer &commandBuffer) { void Record(GPU &gpu, vk::raii::CommandBuffer &commandBuffer) {
// Resolve descriptor infos from dynamic bindings // Resolve descriptor infos from dynamic bindings
for (size_t i{}; i < updateInfo->bufferDescDynamicBindings.size(); i++) { for (size_t i{}; i < updateInfo->bufferDescDynamicBindings.size(); i++) {
@ -332,7 +333,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
} }
void SetIndexBuffer(const BufferBinding &binding, vk::IndexType indexType) { void SetIndexBuffer(const BufferBinding &binding, vk::IndexType indexType) {
AppendCmd<SetIndexBufferCmd>({ AppendCmd<SetIndexBufferCmd>(
{
.indexType = indexType, .indexType = indexType,
.buffer = binding.buffer, .buffer = binding.buffer,
.offset = binding.offset, .offset = binding.offset,
@ -342,14 +344,16 @@ namespace skyline::gpu::interconnect::maxwell3d {
void SetIndexBuffer(BufferView view, vk::IndexType indexType) { void SetIndexBuffer(BufferView view, vk::IndexType indexType) {
view.GetBuffer()->BlockSequencedCpuBackingWrites(); view.GetBuffer()->BlockSequencedCpuBackingWrites();
AppendCmd<SetIndexBufferDynamicCmd>({ AppendCmd<SetIndexBufferDynamicCmd>(
{
.base.indexType = indexType, .base.indexType = indexType,
.view = view, .view = view,
}); });
} }
void SetTransformFeedbackBuffer(u32 index, const BufferBinding &binding) { void SetTransformFeedbackBuffer(u32 index, const BufferBinding &binding) {
AppendCmd<SetTransformFeedbackBufferCmd>({ AppendCmd<SetTransformFeedbackBufferCmd>(
{
.binding = index, .binding = index,
.buffer = binding.buffer, .buffer = binding.buffer,
.offset = binding.offset, .offset = binding.offset,
@ -359,34 +363,39 @@ namespace skyline::gpu::interconnect::maxwell3d {
void SetTransformFeedbackBuffer(u32 index, BufferView view) { void SetTransformFeedbackBuffer(u32 index, BufferView view) {
view.GetBuffer()->BlockSequencedCpuBackingWrites(); view.GetBuffer()->BlockSequencedCpuBackingWrites();
AppendCmd<SetTransformFeedbackBufferDynamicCmd>({ AppendCmd<SetTransformFeedbackBufferDynamicCmd>(
{
.base.binding = index, .base.binding = index,
.view = view, .view = view,
}); });
} }
void SetViewport(u32 index, const vk::Viewport &viewport) { void SetViewport(u32 index, const vk::Viewport &viewport) {
AppendCmd<SetViewportCmd>({ AppendCmd<SetViewportCmd>(
{
.index = index, .index = index,
.viewport = viewport, .viewport = viewport,
}); });
} }
void SetScissor(u32 index, const vk::Rect2D &scissor) { void SetScissor(u32 index, const vk::Rect2D &scissor) {
AppendCmd<SetScissorCmd>({ AppendCmd<SetScissorCmd>(
{
.index = index, .index = index,
.scissor = scissor, .scissor = scissor,
}); });
} }
void SetLineWidth(float lineWidth) { void SetLineWidth(float lineWidth) {
AppendCmd<SetLineWidthCmd>({ AppendCmd<SetLineWidthCmd>(
{
.lineWidth = lineWidth, .lineWidth = lineWidth,
}); });
} }
void SetDepthBias(float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) { void SetDepthBias(float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) {
AppendCmd<SetDepthBiasCmd>({ AppendCmd<SetDepthBiasCmd>(
{
.depthBiasConstantFactor = depthBiasConstantFactor, .depthBiasConstantFactor = depthBiasConstantFactor,
.depthBiasClamp = depthBiasClamp, .depthBiasClamp = depthBiasClamp,
.depthBiasSlopeFactor = depthBiasSlopeFactor, .depthBiasSlopeFactor = depthBiasSlopeFactor,
@ -394,20 +403,23 @@ namespace skyline::gpu::interconnect::maxwell3d {
} }
void SetBlendConstants(const std::array<float, engine::BlendColorChannelCount> &blendConstants) { void SetBlendConstants(const std::array<float, engine::BlendColorChannelCount> &blendConstants) {
AppendCmd<SetBlendConstantsCmd>({ AppendCmd<SetBlendConstantsCmd>(
{
.blendConstants = blendConstants, .blendConstants = blendConstants,
}); });
} }
void SetDepthBounds(float minDepthBounds, float maxDepthBounds) { void SetDepthBounds(float minDepthBounds, float maxDepthBounds) {
AppendCmd<SetDepthBoundsCmd>({ AppendCmd<SetDepthBoundsCmd>(
{
.minDepthBounds = minDepthBounds, .minDepthBounds = minDepthBounds,
.maxDepthBounds = maxDepthBounds, .maxDepthBounds = maxDepthBounds,
}); });
} }
void SetBaseStencilState(vk::StencilFaceFlags flags, u32 funcRef, u32 funcMask, u32 mask) { void SetBaseStencilState(vk::StencilFaceFlags flags, u32 funcRef, u32 funcMask, u32 mask) {
AppendCmd<SetBaseStencilStateCmd>({ AppendCmd<SetBaseStencilStateCmd>(
{
.flags = flags, .flags = flags,
.funcRef = funcRef, .funcRef = funcRef,
.funcMask = funcMask, .funcMask = funcMask,
@ -416,7 +428,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
} }
void SetDescriptorSetWithUpdate(DescriptorUpdateInfo *updateInfo, DescriptorAllocator::ActiveDescriptorSet *dstSet, DescriptorAllocator::ActiveDescriptorSet *srcSet) { void SetDescriptorSetWithUpdate(DescriptorUpdateInfo *updateInfo, DescriptorAllocator::ActiveDescriptorSet *dstSet, DescriptorAllocator::ActiveDescriptorSet *srcSet) {
AppendCmd<SetDescriptorSetWithUpdateCmd>({ AppendCmd<SetDescriptorSetWithUpdateCmd>(
{
.updateInfo = updateInfo, .updateInfo = updateInfo,
.srcSet = srcSet, .srcSet = srcSet,
.dstSet = dstSet, .dstSet = dstSet,
@ -424,9 +437,17 @@ namespace skyline::gpu::interconnect::maxwell3d {
} }
void SetPipeline(vk::Pipeline pipeline) { void SetPipeline(vk::Pipeline pipeline) {
AppendCmd<SetPipelineCmd>({ AppendCmd<SetPipelineCmd>(
{
.pipeline = pipeline, .pipeline = pipeline,
}); });
} }
void SetDescriptorSetWithPush(DescriptorUpdateInfo *updateInfo) {
AppendCmd<SetDescriptorSetWithPushCmd>(
{
.updateInfo = updateInfo,
});
}
}; };
} }

View File

@ -200,7 +200,6 @@ namespace skyline::gpu::interconnect {
e16to1 = 7, e16to1 = 7,
}; };
// 0x00 // 0x00
struct FormatWord { struct FormatWord {
static constexpr u32 FormatColorComponentPadMask{(1U << 31) | 0b111'111'111'111'1111111U}; //!< Mask for the format, component and pad fields static constexpr u32 FormatColorComponentPadMask{(1U << 31) | 0b111'111'111'111'1111111U}; //!< Mask for the format, component and pad fields

View File

@ -112,7 +112,7 @@ namespace skyline::gpu::interconnect {
}; };
public: public:
bool operator==(const TextureSamplerControl&) const = default; bool operator==(const TextureSamplerControl &) const = default;
float MaxAnisotropy() { float MaxAnisotropy() {
constexpr size_t AnisotropyCount{8}; //!< The amount of unique anisotropy values that can be represented (2^3 — 3-bit value) constexpr size_t AnisotropyCount{8}; //!< The amount of unique anisotropy values that can be represented (2^3 — 3-bit value)