Reformat maxwell3d interconnect codebase

This commit is contained in:
Billy Laws 2022-10-09 13:57:47 +01:00
parent 3766be59e7
commit 62a165b51e
10 changed files with 153 additions and 133 deletions

View File

@ -15,7 +15,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
};
private:
dirty::BoundSubresource<EngineRegisters> engine;
dirty::BoundSubresource <EngineRegisters> engine;
public:
ConstantBufferSelectorState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine);
@ -32,7 +32,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
struct ConstantBuffer {
BufferView view;
void Read(CommandExecutor &executor, span<u8> dstBuffer, size_t srcOffset);
void Read(CommandExecutor &executor, span <u8> dstBuffer, size_t srcOffset);
template<typename T>
T Read(CommandExecutor &executor, size_t srcOffset) {
@ -49,7 +49,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
*/
class ConstantBuffers {
private:
dirty::ManualDirtyState<ConstantBufferSelectorState> selectorState;
dirty::ManualDirtyState <ConstantBufferSelectorState> selectorState;
public:
ConstantBufferSet boundConstantBuffers;
@ -68,7 +68,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
void MarkAllDirty();
void Load(InterconnectContext &ctx, span<u32> data, u32 offset);
void Load(InterconnectContext &ctx, span <u32> data, u32 offset);
void Bind(InterconnectContext &ctx, engine::ShaderStage stage, size_t index);

View File

@ -174,8 +174,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
ctx.gpu.shader.ResetPools();
using PipelineStage = engine::Pipeline::Shader::Type;
auto pipelineStage{[](size_t i){ return static_cast<PipelineStage>(i); }};
auto stageIdx{[](PipelineStage stage){ return static_cast<u8>(stage); }};
auto pipelineStage{[](size_t i) { return static_cast<PipelineStage>(i); }};
auto stageIdx{[](PipelineStage stage) { return static_cast<u8>(stage); }};
std::array<Shader::IR::Program, engine::PipelineCount> programs;
bool ignoreVertexCullBeforeFetch{};
@ -435,9 +435,11 @@ namespace skyline::gpu::interconnect::maxwell3d {
});
if (binding.GetInputRate() == vk::VertexInputRate::eInstance) {
if (!ctx.gpu.traits.supportsVertexAttributeDivisor) [[unlikely]]
if (!ctx.gpu.traits.supportsVertexAttributeDivisor)
[[unlikely]]
Logger::Warn("Vertex attribute divisor used on guest without host support");
else if (!ctx.gpu.traits.supportsVertexAttributeZeroDivisor && binding.divisor == 0) [[unlikely]]
else if (!ctx.gpu.traits.supportsVertexAttributeZeroDivisor && binding.divisor == 0)
[[unlikely]]
Logger::Warn("Vertex attribute zero divisor used on guest without host support");
else
bindingDivisorDescs.push_back({
@ -668,7 +670,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
size_t primaryCbufOffset{desc.cbuf_offset + elemOffset};
u32 primaryVal{primaryCbuf.Read<u32>(ctx.executor, primaryCbufOffset)};
if constexpr (requires { desc.has_secondary; } ) {
if constexpr (requires { desc.has_secondary; }) {
if (desc.has_secondary) {
ConstantBuffer &secondaryCbuf{constantBuffers[desc.secondary_cbuf_index]};
size_t secondaryCbufOffset{desc.secondary_cbuf_offset + elemOffset};
@ -677,7 +679,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
}
}
return { .raw = primaryVal };
return {.raw = primaryVal};
}
static vk::DescriptorImageInfo GetTextureBinding(InterconnectContext &ctx, const Shader::TextureDescriptor &desc, Samplers &samplers, Textures &textures, BindlessHandle handle) {

View File

@ -207,5 +207,4 @@ namespace skyline::gpu::interconnect::maxwell3d {
return sampler.get();
}
}

View File

@ -39,7 +39,6 @@ namespace skyline::gpu::interconnect::maxwell3d {
tsl::robin_map<TextureSamplerControl, std::unique_ptr<vk::raii::Sampler>, util::ObjectHash<TextureSamplerControl>> texSamplerStore;
std::vector<vk::raii::Sampler *> texSamplerCache;
public:
Samplers(DirtyManager &manager, const SamplerPoolState::EngineRegisters &engine);

View File

@ -184,7 +184,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
};
using SetBaseStencilStateCmd = CmdHolder<SetBaseStencilStateCmdImpl>;
struct SetDescriptorSetWithUpdateCmdImpl {
template<bool PushDescriptor>
struct SetDescriptorSetCmdImpl {
void Record(GPU &gpu, vk::raii::CommandBuffer &commandBuffer) {
// Resolve descriptor infos from dynamic bindings
for (size_t i{}; i < updateInfo->bufferDescDynamicBindings.size(); i++) {
@ -332,7 +333,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
}
void SetIndexBuffer(const BufferBinding &binding, vk::IndexType indexType) {
AppendCmd<SetIndexBufferCmd>({
AppendCmd<SetIndexBufferCmd>(
{
.indexType = indexType,
.buffer = binding.buffer,
.offset = binding.offset,
@ -342,14 +344,16 @@ namespace skyline::gpu::interconnect::maxwell3d {
void SetIndexBuffer(BufferView view, vk::IndexType indexType) {
view.GetBuffer()->BlockSequencedCpuBackingWrites();
AppendCmd<SetIndexBufferDynamicCmd>({
AppendCmd<SetIndexBufferDynamicCmd>(
{
.base.indexType = indexType,
.view = view,
});
}
void SetTransformFeedbackBuffer(u32 index, const BufferBinding &binding) {
AppendCmd<SetTransformFeedbackBufferCmd>({
AppendCmd<SetTransformFeedbackBufferCmd>(
{
.binding = index,
.buffer = binding.buffer,
.offset = binding.offset,
@ -359,34 +363,39 @@ namespace skyline::gpu::interconnect::maxwell3d {
void SetTransformFeedbackBuffer(u32 index, BufferView view) {
view.GetBuffer()->BlockSequencedCpuBackingWrites();
AppendCmd<SetTransformFeedbackBufferDynamicCmd>({
AppendCmd<SetTransformFeedbackBufferDynamicCmd>(
{
.base.binding = index,
.view = view,
});
}
void SetViewport(u32 index, const vk::Viewport &viewport) {
AppendCmd<SetViewportCmd>({
AppendCmd<SetViewportCmd>(
{
.index = index,
.viewport = viewport,
});
}
void SetScissor(u32 index, const vk::Rect2D &scissor) {
AppendCmd<SetScissorCmd>({
AppendCmd<SetScissorCmd>(
{
.index = index,
.scissor = scissor,
});
}
void SetLineWidth(float lineWidth) {
AppendCmd<SetLineWidthCmd>({
AppendCmd<SetLineWidthCmd>(
{
.lineWidth = lineWidth,
});
}
void SetDepthBias(float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) {
AppendCmd<SetDepthBiasCmd>({
AppendCmd<SetDepthBiasCmd>(
{
.depthBiasConstantFactor = depthBiasConstantFactor,
.depthBiasClamp = depthBiasClamp,
.depthBiasSlopeFactor = depthBiasSlopeFactor,
@ -394,20 +403,23 @@ namespace skyline::gpu::interconnect::maxwell3d {
}
void SetBlendConstants(const std::array<float, engine::BlendColorChannelCount> &blendConstants) {
AppendCmd<SetBlendConstantsCmd>({
AppendCmd<SetBlendConstantsCmd>(
{
.blendConstants = blendConstants,
});
}
void SetDepthBounds(float minDepthBounds, float maxDepthBounds) {
AppendCmd<SetDepthBoundsCmd>({
AppendCmd<SetDepthBoundsCmd>(
{
.minDepthBounds = minDepthBounds,
.maxDepthBounds = maxDepthBounds,
});
}
void SetBaseStencilState(vk::StencilFaceFlags flags, u32 funcRef, u32 funcMask, u32 mask) {
AppendCmd<SetBaseStencilStateCmd>({
AppendCmd<SetBaseStencilStateCmd>(
{
.flags = flags,
.funcRef = funcRef,
.funcMask = funcMask,
@ -416,7 +428,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
}
void SetDescriptorSetWithUpdate(DescriptorUpdateInfo *updateInfo, DescriptorAllocator::ActiveDescriptorSet *dstSet, DescriptorAllocator::ActiveDescriptorSet *srcSet) {
AppendCmd<SetDescriptorSetWithUpdateCmd>({
AppendCmd<SetDescriptorSetWithUpdateCmd>(
{
.updateInfo = updateInfo,
.srcSet = srcSet,
.dstSet = dstSet,
@ -424,9 +437,17 @@ namespace skyline::gpu::interconnect::maxwell3d {
}
void SetPipeline(vk::Pipeline pipeline) {
AppendCmd<SetPipelineCmd>({
AppendCmd<SetPipelineCmd>(
{
.pipeline = pipeline,
});
}
void SetDescriptorSetWithPush(DescriptorUpdateInfo *updateInfo) {
AppendCmd<SetDescriptorSetWithPushCmd>(
{
.updateInfo = updateInfo,
});
}
};
}

View File

@ -200,7 +200,6 @@ namespace skyline::gpu::interconnect {
e16to1 = 7,
};
// 0x00
struct FormatWord {
static constexpr u32 FormatColorComponentPadMask{(1U << 31) | 0b111'111'111'111'1111111U}; //!< Mask for the format, component and pad fields

View File

@ -112,7 +112,7 @@ namespace skyline::gpu::interconnect {
};
public:
bool operator==(const TextureSamplerControl&) const = default;
bool operator==(const TextureSamplerControl &) const = default;
float MaxAnisotropy() {
constexpr size_t AnisotropyCount{8}; //!< The amount of unique anisotropy values that can be represented (2^3 — 3-bit value)