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https://github.com/skyline-emu/skyline.git
synced 2024-11-10 22:05:07 +01:00
Implement Maxwell3D Depth/Stencil State
Implements the entirety of Maxwell3D Depth/Stencil state for both faces including compare/write masks and reference value. Maxwell3D register `stencilTwoSideEnable` is ignored as its behavior is unknown and could mean the same behavior for both stencils or the back facing stencil being disabled as a result of this it is unimplemented.
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@ -2052,6 +2052,151 @@ namespace skyline::gpu::interconnect {
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/* Depth */
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/* Depth */
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vk::PipelineDepthStencilStateCreateInfo depthState{};
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vk::PipelineDepthStencilStateCreateInfo depthState{};
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void SetDepthTestEnabled(bool enabled) {
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depthState.depthTestEnable = enabled;
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}
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vk::CompareOp ConvertCompareOp(maxwell3d::CompareOp op) {
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using MaxwellOp = maxwell3d::CompareOp;
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using VkOp = vk::CompareOp;
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switch (op) {
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case MaxwellOp::Never:
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case MaxwellOp::NeverGL:
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return VkOp::eNever;
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case MaxwellOp::Less:
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case MaxwellOp::LessGL:
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return VkOp::eLess;
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case MaxwellOp::Equal:
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case MaxwellOp::EqualGL:
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return VkOp::eEqual;
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case MaxwellOp::LessOrEqual:
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case MaxwellOp::LessOrEqualGL:
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return VkOp::eLessOrEqual;
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case MaxwellOp::Greater:
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case MaxwellOp::GreaterGL:
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return VkOp::eGreater;
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case MaxwellOp::NotEqual:
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case MaxwellOp::NotEqualGL:
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return VkOp::eNotEqual;
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case MaxwellOp::GreaterOrEqual:
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case MaxwellOp::GreaterOrEqualGL:
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return VkOp::eGreaterOrEqual;
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case MaxwellOp::Always:
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case MaxwellOp::AlwaysGL:
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return VkOp::eAlways;
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}
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}
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void SetDepthTestFunction(maxwell3d::CompareOp function) {
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depthState.depthCompareOp = ConvertCompareOp(function);
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}
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void SetDepthWriteEnabled(bool enabled) {
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depthState.depthWriteEnable = enabled;
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}
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void SetDepthBoundsTestEnabled(bool enabled) {
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depthState.depthBoundsTestEnable = enabled;
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}
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void SetMinDepthBounds(float min) {
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depthState.minDepthBounds = min;
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}
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void SetMaxDepthBounds(float max) {
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depthState.maxDepthBounds = max;
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}
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void SetStencilTestEnabled(bool enabled) {
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depthState.stencilTestEnable = enabled;
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}
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vk::StencilOp ConvertStencilOp(maxwell3d::StencilOp op) {
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using MaxwellOp = maxwell3d::StencilOp;
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using VkOp = vk::StencilOp;
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switch (op) {
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case MaxwellOp::Keep:
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return VkOp::eKeep;
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case MaxwellOp::Zero:
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return VkOp::eZero;
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case MaxwellOp::Replace:
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return VkOp::eReplace;
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case MaxwellOp::IncrementAndClamp:
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return VkOp::eIncrementAndClamp;
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case MaxwellOp::DecrementAndClamp:
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return VkOp::eDecrementAndClamp;
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case MaxwellOp::Invert:
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return VkOp::eInvert;
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case MaxwellOp::IncrementAndWrap:
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return VkOp::eIncrementAndWrap;
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case MaxwellOp::DecrementAndWrap:
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return VkOp::eDecrementAndWrap;
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}
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}
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void SetStencilFrontFailOp(maxwell3d::StencilOp op) {
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depthState.front.failOp = ConvertStencilOp(op);
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}
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void SetStencilBackFailOp(maxwell3d::StencilOp op) {
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depthState.back.failOp = ConvertStencilOp(op);
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}
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void SetStencilFrontPassOp(maxwell3d::StencilOp op) {
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depthState.front.passOp = ConvertStencilOp(op);
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}
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void SetStencilBackPassOp(maxwell3d::StencilOp op) {
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depthState.back.passOp = ConvertStencilOp(op);
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}
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void SetStencilFrontDepthFailOp(maxwell3d::StencilOp op) {
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depthState.front.depthFailOp = ConvertStencilOp(op);
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}
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void SetStencilBackDepthFailOp(maxwell3d::StencilOp op) {
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depthState.back.depthFailOp = ConvertStencilOp(op);
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}
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void SetStencilFrontCompareOp(maxwell3d::CompareOp op) {
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depthState.front.compareOp = ConvertCompareOp(op);
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}
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void SetStencilBackCompareOp(maxwell3d::CompareOp op) {
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depthState.back.compareOp = ConvertCompareOp(op);
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}
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void SetStencilFrontCompareMask(u32 mask) {
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depthState.front.compareMask = mask;
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}
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void SetStencilBackCompareMask(u32 mask) {
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depthState.back.compareMask = mask;
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}
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void SetStencilFrontWriteMask(u32 mask) {
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depthState.front.writeMask = mask;
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}
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void SetStencilBackWriteMask(u32 mask) {
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depthState.back.writeMask = mask;
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}
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void SetStencilFrontReference(u32 reference) {
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depthState.front.reference = reference;
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}
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void SetStencilBackReference(u32 reference) {
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depthState.back.reference = reference;
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}
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/* Multisampling */
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/* Multisampling */
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vk::PipelineMultisampleStateCreateInfo multisampleState{
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vk::PipelineMultisampleStateCreateInfo multisampleState{
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.rasterizationSamples = vk::SampleCountFlagBits::e1,
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.rasterizationSamples = vk::SampleCountFlagBits::e1,
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@ -234,6 +234,90 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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context.UpdateRenderTargetControl(renderTargetControl);
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context.UpdateRenderTargetControl(renderTargetControl);
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})
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})
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MAXWELL3D_CASE(depthTestEnable, {
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context.SetDepthTestEnabled(depthTestEnable);
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})
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MAXWELL3D_CASE(depthTestFunc, {
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context.SetDepthTestFunction(depthTestFunc);
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})
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MAXWELL3D_CASE(depthWriteEnable, {
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context.SetDepthWriteEnabled(depthWriteEnable);
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})
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MAXWELL3D_CASE(depthBoundsEnable, {
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context.SetDepthBoundsTestEnabled(depthBoundsEnable);
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})
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MAXWELL3D_CASE(depthBoundsNear, {
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context.SetMinDepthBounds(depthBoundsNear);
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})
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MAXWELL3D_CASE(depthBoundsFar, {
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context.SetMaxDepthBounds(depthBoundsFar);
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})
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MAXWELL3D_CASE(stencilEnable, {
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context.SetStencilTestEnabled(stencilEnable);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, failOp, {
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context.SetStencilFrontFailOp(failOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, zFailOp, {
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context.SetStencilFrontDepthFailOp(zFailOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, passOp, {
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context.SetStencilFrontPassOp(passOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, compareOp, {
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context.SetStencilFrontCompareOp(compareOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, compareReference, {
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context.SetStencilFrontReference(compareReference);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, compareMask, {
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context.SetStencilFrontCompareMask(compareMask);
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})
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MAXWELL3D_STRUCT_CASE(stencilFront, writeMask, {
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context.SetStencilFrontWriteMask(writeMask);
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})
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MAXWELL3D_STRUCT_CASE(stencilBack, failOp, {
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context.SetStencilBackFailOp(failOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilBack, zFailOp, {
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context.SetStencilBackDepthFailOp(zFailOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilBack, passOp, {
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context.SetStencilBackPassOp(passOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilBack, compareOp, {
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context.SetStencilBackCompareOp(compareOp);
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})
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MAXWELL3D_STRUCT_CASE(stencilBackExtra, compareReference, {
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context.SetStencilBackReference(compareReference);
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})
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MAXWELL3D_STRUCT_CASE(stencilBackExtra, compareMask, {
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context.SetStencilBackCompareMask(compareMask);
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})
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MAXWELL3D_STRUCT_CASE(stencilBackExtra, writeMask, {
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context.SetStencilBackWriteMask(writeMask);
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})
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MAXWELL3D_CASE(independentBlendEnable, {
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MAXWELL3D_CASE(independentBlendEnable, {
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context.SetIndependentBlendingEnabled(independentBlendEnable);
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context.SetIndependentBlendingEnabled(independentBlendEnable);
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})
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})
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@ -95,7 +95,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x370, DepthBiasEnable> depthBiasEnable;
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Register<0x370, DepthBiasEnable> depthBiasEnable;
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struct StencilBackExtra {
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struct StencilBackExtra {
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u32 compareRef; // 0x3D5
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u32 compareReference; // 0x3D5
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u32 writeMask; // 0x3D6
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u32 writeMask; // 0x3D6
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u32 compareMask; // 0x3D7
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u32 compareMask; // 0x3D7
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};
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};
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@ -109,6 +109,10 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x3D9, TiledCacheSize> tiledCacheSize;
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Register<0x3D9, TiledCacheSize> tiledCacheSize;
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Register<0x3E4, u32> commonColorWriteMask; //!< If enabled, the color write masks for all RTs must be set to that of the first RT
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Register<0x3E4, u32> commonColorWriteMask; //!< If enabled, the color write masks for all RTs must be set to that of the first RT
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Register<0x3E7, float> depthBoundsNear;
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Register<0x3E8, float> depthBoundsFar;
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Register<0x3EB, u32> rtSeparateFragData;
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Register<0x3EB, u32> rtSeparateFragData;
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Register<0x3F8, type::Address> depthTargetAddress;
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Register<0x3F8, type::Address> depthTargetAddress;
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@ -117,13 +121,16 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x3FC, u32> depthTargetLayerStride;
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Register<0x3FC, u32> depthTargetLayerStride;
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Register<0x458, std::array<type::VertexAttribute, type::VertexAttributeCount>> vertexAttributeState;
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Register<0x458, std::array<type::VertexAttribute, type::VertexAttributeCount>> vertexAttributeState;
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Register<0x487, type::RenderTargetControl> renderTargetControl;
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Register<0x487, type::RenderTargetControl> renderTargetControl;
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Register<0x48A, u32> depthTargetWidth;
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Register<0x48A, u32> depthTargetWidth;
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Register<0x48B, u32> depthTargetHeight;
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Register<0x48B, u32> depthTargetHeight;
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Register<0x48C, type::RenderTargetArrayMode> depthTargetArrayMode;
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Register<0x48C, type::RenderTargetArrayMode> depthTargetArrayMode;
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Register<0x4B3, u32> depthTestEnable;
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Register<0x4B9, u32> independentBlendEnable;
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Register<0x4B9, u32> independentBlendEnable;
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Register<0x4BA, u32> depthWriteEnable;
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Register<0x4BB, u32> alphaTestEnable;
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Register<0x4BB, u32> alphaTestEnable;
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Register<0x4C3, type::CompareOp> depthTestFunc;
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Register<0x4C3, type::CompareOp> depthTestFunc;
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Register<0x4C4, float> alphaTestRef;
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Register<0x4C4, float> alphaTestRef;
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@ -158,13 +165,11 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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struct StencilFront {
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struct StencilFront {
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type::StencilOp failOp; // 0x4E1
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type::StencilOp failOp; // 0x4E1
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type::StencilOp zFailOp; // 0x4E2
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type::StencilOp zFailOp; // 0x4E2
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type::StencilOp zPassOp; // 0x4E3
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type::StencilOp passOp; // 0x4E3
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struct {
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type::CompareOp compareOp; // 0x4E4
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type::CompareOp op; // 0x4E4
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u32 compareReference; // 0x4E5
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i32 ref; // 0x4E5
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u32 compareMask; // 0x4E6
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u32 mask; // 0x4E6
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} compare;
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u32 writeMask; // 0x4E7
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u32 writeMask; // 0x4E7
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};
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};
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struct StencilBack {
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struct StencilBack {
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type::StencilOp failOp; // 0x566
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type::StencilOp failOp; // 0x566
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type::StencilOp zFailOp; // 0x567
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type::StencilOp zFailOp; // 0x567
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type::StencilOp zPassOp; // 0x568
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type::StencilOp passOp; // 0x568
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type::CompareOp compareOp; // 0x569
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type::CompareOp compareOp; // 0x569
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};
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};
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Register<0x566, StencilBack> stencilBack;
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Register<0x566, StencilBack> stencilBack;
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@ -239,6 +244,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x64B, u32> viewportTransformEnable;
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Register<0x64B, u32> viewportTransformEnable;
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Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
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Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
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Register<0x66F, u32> depthBoundsEnable;
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struct ColorLogicOp {
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struct ColorLogicOp {
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u32 enable;
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u32 enable;
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type::ColorLogicOp type;
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type::ColorLogicOp type;
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