mirror of
https://github.com/skyline-emu/skyline.git
synced 2024-06-14 16:38:43 +02:00
Move .patch to start of executable (Pre-Patching)
This commit is contained in:
◱ PixelyIon
◱ PixelyIon
parent
369bd469f6
commit
6f2cd41470
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@ -7,6 +7,8 @@
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namespace skyline::kernel {
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MemoryManager::MemoryManager(const DeviceState &state) : state(state) {}
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constexpr size_t RegionAlignment{1ULL << 21}; //!< The minimum alignment of a HOS memory region
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void MemoryManager::InitializeVmm(memory::AddressSpaceType type) {
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switch (type) {
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case memory::AddressSpaceType::AddressSpace32Bit:
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@ -22,7 +24,7 @@ namespace skyline::kernel {
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case memory::AddressSpaceType::AddressSpace39Bit: {
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addressSpace.address = 0;
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addressSpace.size = 1UL << 39;
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base.size = 0x78000000 + 0x1000000000 + 0x180000000 + 0x80000000 + 0x1000000000;
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base.size = 0x78000000 + 0x1000000000 + 0x180000000 + 0x80000000 + 0x1000000000; // Code region size is an assumed maximum here
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break;
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}
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@ -41,7 +43,7 @@ namespace skyline::kernel {
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}
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start = util::HexStringToInt<u64>(std::string_view(maps.data() + maps.find_first_of('-', line) + 1, sizeof(u64) * 2));
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alignedStart = util::AlignUp(start, 1ULL << 21);
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alignedStart = util::AlignUp(start, RegionAlignment);
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if (alignedStart + base.size > addressSpace.size)
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break;
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} while ((line = maps.find_first_of('\n', line)) != std::string::npos && line++);
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@ -49,7 +51,7 @@ namespace skyline::kernel {
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if (!base.address)
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throw exception("Cannot find a suitable carveout for the guest address space");
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mmap(reinterpret_cast<void*>(base.address), base.size, PROT_NONE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
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mmap(reinterpret_cast<void *>(base.address), base.size, PROT_NONE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
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chunks = {ChunkDescriptor{
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.ptr = reinterpret_cast<u8 *>(addressSpace.address),
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@ -60,6 +62,9 @@ namespace skyline::kernel {
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void MemoryManager::InitializeRegions(u8 *codeStart, u64 size) {
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u64 address{reinterpret_cast<u64>(codeStart)};
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if (!util::IsAligned(address, RegionAlignment))
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throw exception("Non-aligned code region was used to initialize regions: 0x{:X} - 0x{:X}", codeStart, codeStart + size);
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switch (addressSpace.size) {
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case 1UL << 36: {
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code.address = base.address;
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@ -79,7 +84,7 @@ namespace skyline::kernel {
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case 1UL << 39: {
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code.address = base.address;
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code.size = 0x78000000;
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code.size = util::AlignUp(size, RegionAlignment);
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alias.address = code.address + code.size;
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alias.size = 0x1000000000;
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heap.address = alias.address + alias.size;
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@ -95,6 +100,12 @@ namespace skyline::kernel {
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throw exception("Regions initialized without VMM initialization");
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}
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auto newSize{code.size + alias.size + stack.size + heap.size + tlsIo.size};
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if (newSize > base.size)
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throw exception("Region size has exceeded pre-allocated area: 0x{:X}/0x{:X}", newSize, base.size);
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if (newSize != base.size)
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munmap(reinterpret_cast<u8 *>(base.address) + base.size, newSize - base.size);
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if (size > code.size)
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throw exception("Code region ({}) is smaller than mapped code size ({})", code.size, size);
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@ -678,11 +678,11 @@ namespace skyline::kernel::svc {
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break;
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case constant::infoState::AddressSpaceBaseAddr:
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out = state.process->memory.addressSpace.address;
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out = state.process->memory.base.address;
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break;
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case constant::infoState::AddressSpaceSize:
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out = state.process->memory.addressSpace.size;
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out = state.process->memory.base.size;
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break;
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case constant::infoState::StackRegionBaseAddr:
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@ -26,7 +26,7 @@ namespace skyline::kernel::type {
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if (ptr && !util::PageAligned(ptr))
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throw exception("KSharedMemory was mapped to a non-page-aligned address: 0x{:X}", ptr);
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guest.ptr = reinterpret_cast<u8 *>(mmap(ptr, size, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_SHARED | (ptr ? MAP_FIXED_NOREPLACE : 0), fd, 0));
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guest.ptr = reinterpret_cast<u8 *>(mmap(ptr, size, permission.Get(), MAP_SHARED | (ptr ? MAP_FIXED : 0), fd, 0));
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if (guest.ptr == MAP_FAILED)
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throw exception("An error occurred while mapping shared memory in guest");
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guest.size = size;
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@ -21,30 +21,25 @@ namespace skyline::loader {
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if (!util::PageAligned(executable.text.offset) || !util::PageAligned(executable.ro.offset) || !util::PageAligned(executable.data.offset))
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throw exception("LoadProcessData: Section offsets are not aligned with page size: 0x{:X}, 0x{:X}, 0x{:X}", executable.text.offset, executable.ro.offset, executable.data.offset);
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// The data section will always be the last section in memory, so put the patch section after it
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u64 patchOffset{executable.data.offset + dataSize};
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std::vector<u32> patch = state.nce->PatchCode(executable.text.contents, reinterpret_cast<u64>(base), patchOffset);
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auto patch{state.nce->GetPatchData(executable.text.contents)};
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u64 patchSize{patch.size() * sizeof(u32)};
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u64 padding{util::AlignUp(patchSize, PAGE_SIZE) - patchSize};
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process->NewHandle<kernel::type::KPrivateMemory>(base, patch.size, memory::Permission{false, false, false}, memory::states::Reserved); // ---
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state.logger->Debug("Successfully mapped section .patch @ 0x{:X}, Size = 0x{:X}", base, patch.size);
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process->NewHandle<kernel::type::KPrivateMemory>(base + executable.text.offset, textSize, memory::Permission{true, false, true}, memory::states::CodeStatic); // R-X
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state.logger->Debug("Successfully mapped section .text @ {}, Size = 0x{:X}", base + executable.text.offset, textSize);
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process->NewHandle<kernel::type::KPrivateMemory>(base + patch.size + executable.text.offset, textSize, memory::Permission{true, false, true}, memory::states::CodeStatic); // R-X
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state.logger->Debug("Successfully mapped section .text @ 0x{:X}, Size = 0x{:X}", base + patch.size + executable.text.offset, textSize);
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process->NewHandle<kernel::type::KPrivateMemory>(base + executable.ro.offset, roSize, memory::Permission{true, false, false}, memory::states::CodeReadOnly); // R--
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state.logger->Debug("Successfully mapped section .rodata @ {}, Size = 0x{:X}", base + executable.ro.offset, roSize);
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process->NewHandle<kernel::type::KPrivateMemory>(base + patch.size + executable.ro.offset, roSize, memory::Permission{true, false, false}, memory::states::CodeReadOnly); // R--
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state.logger->Debug("Successfully mapped section .rodata @ 0x{:X}, Size = 0x{:X}", base + patch.size + executable.ro.offset, roSize);
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process->NewHandle<kernel::type::KPrivateMemory>(base + executable.data.offset, dataSize, memory::Permission{true, true, false}, memory::states::CodeMutable); // RW-
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state.logger->Debug("Successfully mapped section .data @ {}, Size = 0x{:X}", base + executable.data.offset, dataSize);
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process->NewHandle<kernel::type::KPrivateMemory>(base + patch.size + executable.data.offset, dataSize, memory::Permission{true, true, false}, memory::states::CodeMutable); // RW-
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state.logger->Debug("Successfully mapped section .data + .bss @ 0x{:X}, Size = 0x{:X}", base + patch.size + executable.data.offset, dataSize);
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process->NewHandle<kernel::type::KPrivateMemory>(base + patchOffset, patchSize + padding, memory::Permission{true, true, true}, memory::states::CodeMutable); // RWX
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state.logger->Debug("Successfully mapped section .patch @ {}, Size = 0x{:X}", base + patchOffset, patchSize + padding);
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state.nce->PatchCode(executable.text.contents, reinterpret_cast<u32*>(base), patch.size, patch.offsets);
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std::memcpy(base + patch.size + executable.text.offset, executable.text.contents.data(), textSize);
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std::memcpy(base + patch.size + executable.ro.offset, executable.ro.contents.data(), roSize);
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std::memcpy(base + patch.size + executable.data.offset, executable.data.contents.data(), dataSize - executable.bssSize);
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std::memcpy(base + executable.text.offset, executable.text.contents.data(), textSize);
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std::memcpy(base + executable.ro.offset, executable.ro.contents.data(), roSize);
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std::memcpy(base + executable.data.offset, executable.data.contents.data(), dataSize - executable.bssSize);
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std::memcpy(base + patchOffset, patch.data(), patchSize);
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return {base, patchOffset + patchSize + padding, base};
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return {base, patch.size + textSize + roSize + dataSize, base + patch.size};
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}
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}
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@ -96,153 +96,185 @@ namespace skyline::nce {
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}
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}
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std::vector<u32> NCE::PatchCode(std::vector<u8> &code, u64 baseAddress, i64 patchBase) {
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constexpr u32 TpidrEl0{0x5E82}; // ID of TPIDR_EL0 in MRS
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constexpr u32 TpidrroEl0{0x5E83}; // ID of TPIDRRO_EL0 in MRS
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constexpr u32 CntfrqEl0{0x5F00}; // ID of CNTFRQ_EL0 in MRS
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constexpr u32 CntpctEl0{0x5F01}; // ID of CNTPCT_EL0 in MRS
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constexpr u32 CntvctEl0{0x5F02}; // ID of CNTVCT_EL0 in MRS
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constexpr u32 TegraX1Freq{19200000}; // The clock frequency of the Tegra X1 (19.2 MHz)
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constexpr size_t MainSvcTrampolineSize{17};
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constexpr u8 MainSvcTrampolineSize{17}; // Size of the main SVC trampoline function in u32 units
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constexpr u32 TpidrEl0{0x5E82}; // ID of TPIDR_EL0 in MRS
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constexpr u32 TpidrroEl0{0x5E83}; // ID of TPIDRRO_EL0 in MRS
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constexpr u32 CntfrqEl0{0x5F00}; // ID of CNTFRQ_EL0 in MRS
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constexpr u32 CntpctEl0{0x5F01}; // ID of CNTPCT_EL0 in MRS
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constexpr u32 CntvctEl0{0x5F02}; // ID of CNTVCT_EL0 in MRS
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constexpr u32 TegraX1Freq{19200000}; // The clock frequency of the Tegra X1 (19.2 MHz)
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size_t index{};
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std::vector<u32> patch(guest::SaveCtxSize + guest::LoadCtxSize + MainSvcTrampolineSize);
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NCE::PatchData NCE::GetPatchData(const std::vector<u8> &text) {
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size_t size{guest::SaveCtxSize + guest::LoadCtxSize + MainSvcTrampolineSize};
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std::vector<size_t> offsets;
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std::memcpy(patch.data(), reinterpret_cast<void *>(&guest::SaveCtx), guest::SaveCtxSize * sizeof(u32));
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index += guest::SaveCtxSize;
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u64 frequency;
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asm("MRS %0, CNTFRQ_EL0" : "=r"(frequency));
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bool rescaleClock{frequency != TegraX1Freq};
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auto start{reinterpret_cast<const u32 *>(text.data())}, end{reinterpret_cast<const u32 *>(text.data() + text.size())};
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for (const u32 *instruction{start}; instruction < end; instruction++) {
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auto svc{*reinterpret_cast<const instr::Svc *>(instruction)};
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auto mrs{*reinterpret_cast<const instr::Mrs *>(instruction)};
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auto msr{*reinterpret_cast<const instr::Msr *>(instruction)};
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if (svc.Verify()) {
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size += 7;
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offsets.push_back(instruction - start);
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} else if (mrs.Verify()) {
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if (mrs.srcReg == TpidrroEl0 || mrs.srcReg == TpidrEl0) {
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size += ((mrs.destReg != regs::X0) ? 6 : 3);
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offsets.push_back(instruction - start);
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} else {
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if (rescaleClock) {
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if (mrs.srcReg == CntpctEl0) {
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size += guest::RescaleClockSize + 3;
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offsets.push_back(instruction - start);
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} else if (mrs.srcReg == CntfrqEl0) {
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size += 3;
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offsets.push_back(instruction - start);
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}
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} else if (mrs.srcReg == CntpctEl0) {
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offsets.push_back(instruction - start);
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}
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}
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} else if (msr.Verify() && msr.destReg == TpidrEl0) {
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size += 6;
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offsets.push_back(instruction - start);
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}
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}
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return {util::AlignUp(size * sizeof(u32), PAGE_SIZE), offsets};
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}
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void NCE::PatchCode(std::vector<u8> &text, u32 *patch, size_t patchSize, const std::vector<size_t> &offsets) {
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u32 *start{patch};
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u32 *end{patch + (patchSize / sizeof(u32))};
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std::memcpy(patch, reinterpret_cast<void *>(&guest::SaveCtx), guest::SaveCtxSize * sizeof(u32));
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patch += guest::SaveCtxSize;
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{
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/* Main SVC Trampoline */
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/* Store LR in 16B of pre-allocated stack */
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patch[index++] = 0xF90007FE; // STR LR, [SP, #8]
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*patch++ = 0xF90007FE; // STR LR, [SP, #8]
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/* Replace Skyline TLS with host TLS */
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patch[index++] = 0xD53BD041; // MRS X1, TPIDR_EL0
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patch[index++] = 0xF9415022; // LDR X2, [X1, #0x2A0] (ThreadContext::hostTpidrEl0)
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*patch++ = 0xD53BD041; // MRS X1, TPIDR_EL0
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*patch++ = 0xF9415022; // LDR X2, [X1, #0x2A0] (ThreadContext::hostTpidrEl0)
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/* Replace guest stack with host stack */
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patch[index++] = 0xD51BD042; // MSR TPIDR_EL0, X2
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patch[index++] = 0x910003E2; // MOV X2, SP
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patch[index++] = 0xF9415423; // LDR X3, [X1, #0x2A8] (ThreadContext::hostSp)
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patch[index++] = 0x9100007F; // MOV SP, X3
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*patch++ = 0xD51BD042; // MSR TPIDR_EL0, X2
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*patch++ = 0x910003E2; // MOV X2, SP
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*patch++ = 0xF9415423; // LDR X3, [X1, #0x2A8] (ThreadContext::hostSp)
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*patch++ = 0x9100007F; // MOV SP, X3
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/* Store Skyline TLS + guest SP on stack */
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patch[index++] = 0xA9BF0BE1; // STP X1, X2, [SP, #-16]!
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*patch++ = 0xA9BF0BE1; // STP X1, X2, [SP, #-16]!
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/* Jump to SvcHandler */
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for (const auto &mov : instr::MoveRegister(regs::X2, reinterpret_cast<u64>(&NCE::SvcHandler)))
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if (mov)
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patch[index++] = mov;
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patch[index++] = 0xD63F0040; // BLR X2
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*patch++ = mov;
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*patch++ = 0xD63F0040; // BLR X2
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/* Restore Skyline TLS + guest SP */
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patch[index++] = 0xA8C10BE1; // LDP X1, X2, [SP], #16
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patch[index++] = 0xD51BD041; // MSR TPIDR_EL0, X1
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patch[index++] = 0x9100005F; // MOV SP, X2
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*patch++ = 0xA8C10BE1; // LDP X1, X2, [SP], #16
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*patch++ = 0xD51BD041; // MSR TPIDR_EL0, X1
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*patch++ = 0x9100005F; // MOV SP, X2
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/* Restore LR and Return */
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patch[index++] = 0xF94007FE; // LDR LR, [SP, #8]
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patch[index++] = 0xD65F03C0; // RET
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*patch++ = 0xF94007FE; // LDR LR, [SP, #8]
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*patch++ = 0xD65F03C0; // RET
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}
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std::memcpy(patch.data() + index, reinterpret_cast<void *>(&guest::LoadCtx), guest::LoadCtxSize * sizeof(u32));
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index += guest::LoadCtxSize;
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std::memcpy(patch, reinterpret_cast<void *>(&guest::LoadCtx), guest::LoadCtxSize * sizeof(u32));
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patch += guest::LoadCtxSize;
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u64 frequency;
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asm("MRS %0, CNTFRQ_EL0" : "=r"(frequency));
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bool rescaleClock{frequency != TegraX1Freq};
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i64 patchOffset{patchBase / i64(sizeof(u32))};
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u32 *start{reinterpret_cast<u32 *>(code.data())};
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u32 *end{start + (code.size() / sizeof(u32))};
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for (u32 *instruction{start}; instruction < end; instruction++) {
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for (auto offset : offsets) {
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u32 *instruction{reinterpret_cast<u32 *>(text.data()) + offset};
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auto svc{*reinterpret_cast<instr::Svc *>(instruction)};
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auto mrs{*reinterpret_cast<instr::Mrs *>(instruction)};
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auto msr{*reinterpret_cast<instr::Msr *>(instruction)};
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if (svc.Verify()) {
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/* Per-SVC Trampoline */
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patch.resize(patch.size() + 7);
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/* Rewrite SVC with B to trampoline */
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*instruction = instr::B(patchOffset + index).raw;
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*instruction = instr::B((end - patch) + offset, true).raw;
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/* Save Context */
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patch[index++] = 0xF81F0FFE; // STR LR, [SP, #-16]!
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patch[index] = instr::BL(-index).raw;
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index++;
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*patch++ = 0xF81F0FFE; // STR LR, [SP, #-16]!
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*patch = instr::BL(start - patch).raw;
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patch++;
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/* Jump to main SVC trampoline */
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patch[index++] = instr::Movz(regs::W0, static_cast<u16>(svc.value)).raw;
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patch[index] = instr::BL(guest::SaveCtxSize - index).raw;
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index++;
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*patch++ = instr::Movz(regs::W0, static_cast<u16>(svc.value)).raw;
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*patch = instr::BL((start - patch) + guest::SaveCtxSize).raw;
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patch++;
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/* Restore Context and Return */
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patch[index] = instr::BL(guest::SaveCtxSize + MainSvcTrampolineSize - index).raw;
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index++;
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patch[index++] = 0xF84107FE; // LDR LR, [SP], #16
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patch[index] = instr::B(-(patchOffset + index - 1)).raw;
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index++;
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*patch = instr::BL((start - patch) + guest::SaveCtxSize + MainSvcTrampolineSize).raw;
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patch++;
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*patch++ = 0xF84107FE; // LDR LR, [SP], #16
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*patch = instr::B((end - patch) + offset + 1).raw;
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patch++;
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} else if (mrs.Verify()) {
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if (mrs.srcReg == TpidrroEl0 || mrs.srcReg == TpidrEl0) {
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/* Emulated TLS Register Load */
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patch.resize(patch.size() + ((mrs.destReg != regs::X0) ? 6 : 3));
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/* Rewrite MRS with B to trampoline */
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*instruction = instr::B(patchOffset + index).raw;
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*instruction = instr::B((end - patch) + offset, true).raw;
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/* Allocate Scratch Register */
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if (mrs.destReg != regs::X0)
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patch[index++] = 0xF81F0FE0; // STR X0, [SP, #-16]!
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*patch++ = 0xF81F0FE0; // STR X0, [SP, #-16]!
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/* Retrieve emulated TLS register from ThreadContext */
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patch[index++] = 0xD53BD040; // MRS X0, TPIDR_EL0
|
||||
*patch++ = 0xD53BD040; // MRS X0, TPIDR_EL0
|
||||
if (mrs.srcReg == TpidrroEl0)
|
||||
patch[index++] = 0xF9415800; // LDR X0, [X0, #0x2B0] (ThreadContext::tpidrroEl0)
|
||||
*patch++ = 0xF9415800; // LDR X0, [X0, #0x2B0] (ThreadContext::tpidrroEl0)
|
||||
else
|
||||
patch[index++] = 0xF9415C00; // LDR X0, [X0, #0x2B8] (ThreadContext::tpidrEl0)
|
||||
*patch++ = 0xF9415C00; // LDR X0, [X0, #0x2B8] (ThreadContext::tpidrEl0)
|
||||
|
||||
/* Restore Scratch Register and Return */
|
||||
if (mrs.destReg != regs::X0) {
|
||||
patch[index++] = instr::Mov(regs::X(mrs.destReg), regs::X0).raw;
|
||||
patch[index++] = 0xF84107E0; // LDR X0, [SP], #16
|
||||
*patch++ = instr::Mov(regs::X(mrs.destReg), regs::X0).raw;
|
||||
*patch++ = 0xF84107E0; // LDR X0, [SP], #16
|
||||
}
|
||||
patch[index] = instr::B(-(patchOffset + index - 1)).raw;
|
||||
index++;
|
||||
*patch = instr::B((end - patch) + offset + 1).raw;
|
||||
patch++;
|
||||
} else {
|
||||
if (frequency != TegraX1Freq) {
|
||||
if (rescaleClock) {
|
||||
if (mrs.srcReg == CntpctEl0) {
|
||||
/* Physical Counter Load Emulation (With Rescaling) */
|
||||
patch.resize(patch.size() + guest::RescaleClockSize + 3);
|
||||
|
||||
/* Rewrite MRS with B to trampoline */
|
||||
*instruction = instr::B(patchOffset + index).raw;
|
||||
*instruction = instr::B((end - patch) + offset, true).raw;
|
||||
|
||||
/* Rescale host clock */
|
||||
std::memcpy(patch.data() + index, reinterpret_cast<void *>(&guest::RescaleClock), guest::RescaleClockSize);
|
||||
index += guest::RescaleClockSize;
|
||||
std::memcpy(patch, reinterpret_cast<void *>(&guest::RescaleClock), guest::RescaleClockSize);
|
||||
patch += guest::RescaleClockSize;
|
||||
|
||||
/* Load result from stack into destination register */
|
||||
instr::Ldr ldr(0xF94003E0); // LDR XOUT, [SP]
|
||||
ldr.destReg = mrs.destReg;
|
||||
patch[index++] = ldr.raw;
|
||||
*patch++ = ldr.raw;
|
||||
|
||||
/* Free 32B stack allocation by RescaleClock and Return */
|
||||
patch[index++] = {0x910083FF}; // ADD SP, SP, #32
|
||||
patch[index] = instr::B(-(patchOffset + index - 1)).raw;
|
||||
index++;
|
||||
*patch++ = {0x910083FF}; // ADD SP, SP, #32
|
||||
*patch = instr::B((end - patch) + offset + 1).raw;
|
||||
patch++;
|
||||
} else if (mrs.srcReg == CntfrqEl0) {
|
||||
/* Physical Counter Frequency Load Emulation */
|
||||
patch.resize(patch.size() + 3);
|
||||
|
||||
/* Rewrite MRS with B to trampoline */
|
||||
*instruction = instr::B(patchOffset + index).raw;
|
||||
*instruction = instr::B((end - patch) + offset, true).raw;
|
||||
|
||||
/* Write back Tegra X1 Counter Frequency and Return */
|
||||
for (const auto &mov : instr::MoveRegister(regs::X(mrs.destReg), TegraX1Freq))
|
||||
patch[index++] = mov;
|
||||
patch[index] = instr::B(-(patchOffset + index - 1)).raw;
|
||||
index++;
|
||||
*patch++ = mov;
|
||||
*patch = instr::B((end - patch) + offset + 1).raw;
|
||||
patch++;
|
||||
}
|
||||
} else if (mrs.srcReg == CntpctEl0) {
|
||||
/* Physical Counter Load Emulation (Without Rescaling) */
|
||||
|
|
@ -250,31 +282,25 @@ namespace skyline::nce {
|
|||
*instruction = instr::Mrs(CntvctEl0, regs::X(mrs.destReg)).raw;
|
||||
}
|
||||
}
|
||||
} else if (msr.Verify()) {
|
||||
if (msr.destReg == TpidrEl0) {
|
||||
/* Emulated TLS Register Store */
|
||||
patch.resize(patch.size() + 6);
|
||||
} else if (msr.Verify() && msr.destReg == TpidrEl0) {
|
||||
/* Emulated TLS Register Store */
|
||||
/* Rewrite MSR with B to trampoline */
|
||||
*instruction = instr::B((end - patch) + offset, true).raw;
|
||||
|
||||
/* Rewrite MSR with B to trampoline */
|
||||
*instruction = instr::B(patchOffset + index).raw;
|
||||
/* Allocate Scratch Registers */
|
||||
bool x0x1{mrs.srcReg != regs::X0 && mrs.srcReg != regs::X1};
|
||||
*patch++ = x0x1 ? 0xA9BF07E0 : 0xA9BF0FE2; // STP X(0/2), X(1/3), [SP, #-16]!
|
||||
|
||||
/* Allocate Scratch Registers */
|
||||
bool x0x1{mrs.srcReg != regs::X0 && mrs.srcReg != regs::X1};
|
||||
patch[index++] = x0x1 ? 0xA9BF07E0 : 0xA9BF0FE2; // STP X(0/2), X(1/3), [SP, #-16]!
|
||||
/* Store new TLS value into ThreadContext */
|
||||
*patch++ = x0x1 ? 0xD53BD040 : 0xD53BD042; // MRS X(0/2), TPIDR_EL0
|
||||
*patch++ = instr::Mov(x0x1 ? regs::X1 : regs::X3, regs::X(msr.srcReg)).raw;
|
||||
*patch++ = x0x1 ? 0xF9015C01 : 0xF9015C03; // STR X(1/3), [X0, #0x4B8] (ThreadContext::tpidrEl0)
|
||||
|
||||
/* Store new TLS value into ThreadContext */
|
||||
patch[index++] = x0x1 ? 0xD53BD040 : 0xD53BD042; // MRS X(0/2), TPIDR_EL0
|
||||
patch[index++] = instr::Mov(x0x1 ? regs::X1 : regs::X3, regs::X(msr.srcReg)).raw;
|
||||
patch[index++] = x0x1 ? 0xF9015C01 : 0xF9015C03; // STR X(1/3), [X0, #0x4B8] (ThreadContext::tpidrEl0)
|
||||
|
||||
/* Restore Scratch Registers and Return */
|
||||
patch[index++] = x0x1 ? 0xA8C107E0 : 0xA8C10FE2; // LDP X(0/2), X(1/3), [SP], #16
|
||||
patch[index] = instr::B(-(patchOffset + index - 1)).raw;
|
||||
index++;
|
||||
}
|
||||
/* Restore Scratch Registers and Return */
|
||||
*patch++ = x0x1 ? 0xA8C107E0 : 0xA8C10FE2; // LDP X(0/2), X(1/3), [SP], #16
|
||||
*patch = instr::B((end - patch) + offset + 1).raw;
|
||||
patch++;
|
||||
}
|
||||
patchOffset--;
|
||||
}
|
||||
return patch;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,11 +23,17 @@ namespace skyline::nce {
|
|||
|
||||
void Execute();
|
||||
|
||||
struct PatchData {
|
||||
size_t size; //!< Size of the .patch section
|
||||
std::vector<size_t> offsets; //!< Offsets in .text of instructions that need to be patched
|
||||
};
|
||||
|
||||
static PatchData GetPatchData(const std::vector<u8> &text);
|
||||
|
||||
/**
|
||||
* @brief Generates a patch section for the supplied code
|
||||
* @param baseAddress The address at which the code is mapped
|
||||
* @param patchBase The offset of the patch section from the base address
|
||||
* @brief Writes the .patch section and mutates the code accordingly
|
||||
* @param patch A pointer to the .patch section which should be exactly patchSize in size and located before the .text section
|
||||
*/
|
||||
std::vector<u32> PatchCode(std::vector<u8> &code, u64 baseAddress, i64 patchBase);
|
||||
static void PatchCode(std::vector<u8> &text, u32* patch, size_t patchSize, const std::vector<size_t>& offsets);
|
||||
};
|
||||
}
|
||||
|
|
|
|||
|
|
@ -114,8 +114,8 @@ namespace skyline::nce {
|
|||
/**
|
||||
* @param offset The relative offset to branch to (In 32-bit units)
|
||||
*/
|
||||
constexpr B(i32 offset) {
|
||||
this->offset = offset;
|
||||
constexpr B(i64 offset, bool negate = false) {
|
||||
this->offset = negate ? -offset : offset;
|
||||
sig = 0x5;
|
||||
}
|
||||
|
||||
|
|
@ -307,6 +307,8 @@ namespace skyline::nce {
|
|||
instruction = instr::Movz(destination, offsetValue, offset).raw;
|
||||
zeroed = true;
|
||||
}
|
||||
} else {
|
||||
instruction = 0;
|
||||
}
|
||||
offset++;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user