Implement linked TIC/TSC handle in Maxwell3D

Maxwell3D has a register for linking the TIC/TSC index in bindless texture handles, this is used by games to implement bindless combined texture-sampler handles.
This commit is contained in:
PixelyIon 2022-05-06 14:58:20 +05:30
parent 23a091100d
commit 98c730a644
3 changed files with 14 additions and 0 deletions

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@ -1176,6 +1176,8 @@ namespace skyline::gpu::interconnect {
auto &constantBuffer{pipelineStage.constantBuffers[texture.cbuf_index]};
BindlessTextureHandle handle{constantBuffer.Read<u32>(executor, texture.cbuf_offset)};
if (tscIndexLinked)
handle.samplerIndex = handle.textureIndex;
auto sampler{GetSampler(handle.samplerIndex)};
auto textureView{GetPoolTextureView(handle.textureIndex)};
@ -2292,6 +2294,8 @@ namespace skyline::gpu::interconnect {
/* Samplers */
private:
bool tscIndexLinked{}; //!< If the TSC index in bindless texture handles is the same as the TIC index or if it's independent from the TIC index
struct Sampler : public vk::raii::Sampler, public FenceCycleDependency {
using vk::raii::Sampler::Sampler;
};
@ -2319,6 +2323,10 @@ namespace skyline::gpu::interconnect {
samplerPool.samplerControls = nullptr;
}
void SetTscIndexLinked(bool isTscIndexLinked) {
tscIndexLinked = isTscIndexLinked;
}
private:
vk::Filter ConvertSamplerFilter(TextureSamplerControl::Filter filter) {
using TscFilter = TextureSamplerControl::Filter;

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@ -129,6 +129,10 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
context.SetDepthRenderTargetArrayMode(depthTargetArrayMode);
})
ENGINE_CASE(linkedTscHandle, {
context.SetTscIndexLinked(linkedTscHandle);
});
#define VIEWPORT_TRANSFORM_CALLBACKS(_z, index, data) \
ENGINE_ARRAY_STRUCT_CASE(viewportTransforms, index, scaleX, { \
context.SetViewportX(index, scaleX, registers.viewportTransforms[index].translateX); \

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@ -151,6 +151,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
Register<0x48B, u32> depthTargetHeight;
Register<0x48C, type::RenderTargetArrayMode> depthTargetArrayMode;
Register<0x48D, bool> linkedTscHandle; //!< If enabled, the TSC index in a bindless texture handle is ignored and the TIC index is used as the TSC index, otherwise the TSC index from the bindless texture handle is used
Register<0x4B3, u32> depthTestEnable;
Register<0x4B9, u32> independentBlendEnable;
Register<0x4BA, u32> depthWriteEnable;