mirror of
https://github.com/skyline-emu/skyline.git
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Move nvhost-ctrl-gpu to new device API
This commit is contained in:
Billy Laws
◱ Mark
parent
39492d9365
commit
9bda574a4e
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// SPDX-License-Identifier: MIT OR MPL-2.0
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// Copyright © 2021 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <services/nvdrv/devices/deserialisation/deserialisation.h>
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#include "ctrl_gpu.h"
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namespace skyline::service::nvdrv::device::nvhost {
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CtrlGpu::CtrlGpu(const DeviceState &state, Core &core, const SessionContext &ctx) :
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NvDevice(state, core, ctx),
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errorNotifierEvent(std::make_shared<type::KEvent>(state, false)),
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unknownEvent(std::make_shared<type::KEvent>(state, false)) {}
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PosixResult CtrlGpu::ZCullGetCtxSize(Out<u32> size) {
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size = 0x1;
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return PosixResult::Success;
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}
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PosixResult CtrlGpu::ZCullGetInfo(Out<ZCullInfo> info) {
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info = {};
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return PosixResult::Success;
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}
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PosixResult CtrlGpu::GetCharacteristics(InOut<u64> size, In<u64> userAddress, Out<GpuCharacteristics> characteristics) {
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characteristics = {};
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size = sizeof(GpuCharacteristics);
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return PosixResult::Success;
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}
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PosixResult CtrlGpu::GetTpcMasks(In<u32> bufSize, Out<u64> maskBuf) {
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// TODO
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maskBuf = 0x3;
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return PosixResult::Success;
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}
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PosixResult CtrlGpu::GetActiveSlotMask(Out<u32> slot, Out<u32> mask) {
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slot = 0x7;
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mask = 0x1;
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return PosixResult::Success;
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}
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std::shared_ptr<type::KEvent> CtrlGpu::QueryEvent(u32 eventId) {
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switch (eventId) {
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case 1:
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return errorNotifierEvent;
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case 2:
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return unknownEvent;
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default:
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return nullptr;
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}
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}
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#include <services/nvdrv/devices/deserialisation/macro_def.h>
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static constexpr u32 CtrlGpuMagic{0x47};
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IOCTL_HANDLER_FUNC(CtrlGpu, ({
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IOCTL_CASE_ARGS(OUT, SIZE(0x4), MAGIC(CtrlGpuMagic), FUNC(0x1),
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ZCullGetCtxSize, ARGS(Out<u32>))
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IOCTL_CASE_ARGS(INOUT, SIZE(0x28), MAGIC(CtrlGpuMagic), FUNC(0x2),
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ZCullGetInfo, ARGS(Out<ZCullInfo>))
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IOCTL_CASE_ARGS(INOUT, SIZE(0xB0), MAGIC(CtrlGpuMagic), FUNC(0x5),
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GetCharacteristics, ARGS(InOut<u64>, In<u64>, Out<GpuCharacteristics>))
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IOCTL_CASE_ARGS(INOUT, SIZE(0x18), MAGIC(CtrlGpuMagic), FUNC(0x6),
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GetTpcMasks, ARGS(In<u32>, Pad<u32, 3>, Out<u64>))
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IOCTL_CASE_ARGS(OUT, SIZE(0x8), MAGIC(CtrlGpuMagic), FUNC(0x14),
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GetActiveSlotMask, ARGS(Out<u32>, Out<u32>))
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}))
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#include <services/nvdrv/devices/deserialisation/macro_undef.h>
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}
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// SPDX-License-Identifier: MIT OR MPL-2.0
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// Copyright © 2021 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#pragma once
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#include "services/nvdrv/devices/nvdevice.h"
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namespace skyline::service::nvdrv::device::nvhost {
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/**
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* @brief nvhost::CtrlGpu (/dev/nvhost-ctrl-gpu) is used for context independent operations on the underlying GPU
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* @url https://switchbrew.org/wiki/NV_services#.2Fdev.2Fnvhost-ctrl-gpu
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*/
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class CtrlGpu : public NvDevice {
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private:
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std::shared_ptr<type::KEvent> errorNotifierEvent;
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std::shared_ptr<type::KEvent> unknownEvent;
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public:
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/**
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* @brief Holds hardware characteristics about a GPU, initialised to the GM20B values
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*/
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struct GpuCharacteristics {
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u32 arch{0x120}; // NVGPU_GPU_ARCH_GM200
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u32 impl{0xB}; // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
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u32 rev{0xA1};
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u32 numGpc{0x1};
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u64 l2CacheSize{0x40000};
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u64 onBoardVideoMemorySize{}; // UMA
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u32 numTpcPerGpc{0x2};
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u32 busType{0x20}; // NVGPU_GPU_BUS_TYPE_AXI
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u32 bigPageSize{0x20000};
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u32 compressionPageSize{0x20000};
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u32 pdeCoverageBitCount{0x1B};
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u32 availableBigPageSizes{0x30000};
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u32 gpcMask{0x1};
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u32 smArchSmVersion{0x503}; // Maxwell Generation 5.0.3
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u32 smArchSpaVersion{0x503}; // Maxwell Generation 5.0.3
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u32 smArchWarpCount{0x80};
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u32 gpuVaBitCount{0x28};
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u32 _res_{};
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u64 flags{0x55}; // HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT
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u32 twodClass{0x902D}; // FERMI_TWOD_A
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u32 threedClass{0xB197}; // MAXWELL_B
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u32 computeClass{0xB1C0}; // MAXWELL_COMPUTE_B
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u32 gpfifoClass{0xB06F}; // MAXWELL_CHANNEL_GPFIFO_A
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u32 inlineToMemoryClass{0xA140}; // KEPLER_INLINE_TO_MEMORY_B
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u32 dmaCopyClass{0xA140}; // MAXWELL_DMA_COPY_A
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u32 maxFbpsCount{0x1}; // 0x1
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u32 fbpEnMask{}; // Disabled
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u32 maxLtcPerFbp{0x2};
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u32 maxLtsPerLtc{0x1};
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u32 maxTexPerTpc{}; // Not Supported
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u32 maxGpcCount{0x1};
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u32 ropL2EnMask0{0x21D70}; // fuse_status_opt_rop_l2_fbp_r
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u32 ropL2EnMask1{};
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u64 chipName{util::MakeMagic<u64>("gm20b")};
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u64 grCompbitStoreBaseHw{}; // Not Supported
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};
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/**
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* @brief Contains the Maxwell ZCULL capabilities and configuration
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*/
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struct ZCullInfo {
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u32 widthAlignPixels{0x20};
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u32 heightAlignPixels{0x20};
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u32 pixelSquaresByAliquots{0x400};
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u32 aliquotTotal{0x800};
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u32 regionByteMultiplier{0x20};
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u32 regionHeaderSize{0x20};
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u32 subregionHeaderSize{0xC0};
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u32 subregionWidthAlignPixels{0x20};
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u32 subregionHeightAlignPixels{0x40};
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u32 subregionCount{0x10};
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};
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CtrlGpu(const DeviceState &state, Core &core, const SessionContext &ctx);
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/**
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* @brief Returns the zcull context size
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE
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*/
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PosixResult ZCullGetCtxSize(Out<u32> size);
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/**
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* @brief Returns information about the GPU ZCULL parameters
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_ZCULL_GET_INFO
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*/
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PosixResult ZCullGetInfo(Out<ZCullInfo> info);
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/**
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* @brief Returns a struct with certain GPU characteristics
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS
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*/
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PosixResult GetCharacteristics(InOut<u64> size, In<u64> userAddress, Out<GpuCharacteristics> characteristics);
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/**
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* @brief Returns the TPC mask value for each GPC
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_GET_TPC_MASKS
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*/
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PosixResult GetTpcMasks(In<u32> bufSize, Out<u64> maskBuf);
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/**
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* @brief Returns the mask value for a ZBC slot
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK
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*/
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PosixResult GetActiveSlotMask(Out<u32> slot, Out<u32> mask);
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std::shared_ptr<type::KEvent> QueryEvent(u32 eventId) override;
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PosixResult Ioctl(IoctlDescriptor cmd, span<u8> buffer) override;
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};
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}
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@ -1,130 +0,0 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include "nvhost_ctrl_gpu.h"
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namespace skyline::service::nvdrv::device {
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NvHostCtrlGpu::NvHostCtrlGpu(const DeviceState &state) : errorNotifierEvent(std::make_shared<type::KEvent>(state, false)), unknownEvent(std::make_shared<type::KEvent>(state, false)), NvDevice(state) {}
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NvStatus NvHostCtrlGpu::ZCullGetCtxSize(IoctlType type, span<u8> buffer, span<u8> inlineBuffer) {
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buffer.as<u32>() = 0x1;
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return NvStatus::Success;
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}
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NvStatus NvHostCtrlGpu::ZCullGetInfo(IoctlType type, span<u8> buffer, span<u8> inlineBuffer) {
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struct ZCullInfo {
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u32 widthAlignPixels{0x20};
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u32 heightAlignPixels{0x20};
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u32 pixelSquaresByAliquots{0x400};
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u32 aliquotTotal{0x800};
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u32 regionByteMultiplier{0x20};
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u32 regionHeaderSize{0x20};
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u32 subregionHeaderSize{0xC0};
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u32 subregionWidthAlignPixels{0x20};
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u32 subregionHeightAlignPixels{0x40};
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u32 subregionCount{0x10};
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} zCullInfo;
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buffer.as<ZCullInfo>() = zCullInfo;
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return NvStatus::Success;
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}
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NvStatus NvHostCtrlGpu::GetCharacteristics(IoctlType type, span<u8> buffer, span<u8> inlineBuffer) {
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struct GpuCharacteristics {
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u32 arch{0x120}; // NVGPU_GPU_ARCH_GM200
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u32 impl{0xB}; // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
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u32 rev{0xA1};
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u32 numGpc{0x1};
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u64 l2CacheSize{0x40000};
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u64 onBoardVideoMemorySize{}; // UMA
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u32 numTpcPerGpc{0x2};
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u32 busType{0x20}; // NVGPU_GPU_BUS_TYPE_AXI
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u32 bigPageSize{0x20000};
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u32 compressionPageSize{0x20000};
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u32 pdeCoverageBitCount{0x1B};
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u32 availableBigPageSizes{0x30000};
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u32 gpcMask{0x1};
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u32 smArchSmVersion{0x503}; // Maxwell Generation 5.0.3
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u32 smArchSpaVersion{0x503}; // Maxwell Generation 5.0.3
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u32 smArchWarpCount{0x80};
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u32 gpuVaBitCount{0x28};
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u32 _res_{};
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u64 flags{0x55}; // HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT
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u32 twodClass{0x902D}; // FERMI_TWOD_A
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u32 threedClass{0xB197}; // MAXWELL_B
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u32 computeClass{0xB1C0}; // MAXWELL_COMPUTE_B
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u32 gpfifoClass{0xB06F}; // MAXWELL_CHANNEL_GPFIFO_A
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u32 inlineToMemoryClass{0xA140}; // KEPLER_INLINE_TO_MEMORY_B
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u32 dmaCopyClass{0xA140}; // MAXWELL_DMA_COPY_A
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u32 maxFbpsCount{0x1}; // 0x1
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u32 fbpEnMask{}; // Disabled
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u32 maxLtcPerFbp{0x2};
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u32 maxLtsPerLtc{0x1};
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u32 maxTexPerTpc{}; // Not Supported
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u32 maxGpcCount{0x1};
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u32 ropL2EnMask0{0x21D70}; // fuse_status_opt_rop_l2_fbp_r
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u32 ropL2EnMask1{};
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u64 chipName{util::MakeMagic<u64>("gm20b")};
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u64 grCompbitStoreBaseHw{}; // Not Supported
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};
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struct Data {
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u64 gpuCharacteristicsBufSize; // InOut
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u64 gpuCharacteristicsBufAddr; // In
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GpuCharacteristics gpuCharacteristics; // Out
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} &data = buffer.as<Data>();
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if (data.gpuCharacteristicsBufSize < sizeof(GpuCharacteristics))
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return NvStatus::InvalidSize;
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// The IOCTL3 version of GetCharacteristics additionally outputs to the inline output buffer
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if (type == IoctlType::Ioctl3) {
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auto &inlineCharacteristics{inlineBuffer.as<GpuCharacteristics>()};
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data.gpuCharacteristics = inlineCharacteristics = GpuCharacteristics{};
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} else {
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data.gpuCharacteristics = GpuCharacteristics{};
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}
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data.gpuCharacteristicsBufSize = sizeof(GpuCharacteristics);
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return NvStatus::Success;
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}
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NvStatus NvHostCtrlGpu::GetTpcMasks(IoctlType type, span<u8> buffer, span<u8> inlineBuffer) {
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struct Data {
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u32 maskBufSize; // In
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u32 _res_[3]; // In
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u64 maskBuf; // Out
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} &data = buffer.as<Data>();
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if (data.maskBufSize) {
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if (type == IoctlType::Ioctl3) {
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auto &inlineMask{inlineBuffer.as<u32>()};
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data.maskBuf = inlineMask = 0x3;
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} else {
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data.maskBuf = 0x3;
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}
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}
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return NvStatus::Success;
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}
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NvStatus NvHostCtrlGpu::GetActiveSlotMask(IoctlType type, span<u8> buffer, span<u8> inlineBuffer) {
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struct Data {
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u32 slot{0x07}; // Out
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u32 mask{0x01}; // Out
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} data;
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buffer.as<Data>() = data;
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return NvStatus::Success;
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}
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std::shared_ptr<type::KEvent> NvHostCtrlGpu::QueryEvent(u32 eventId) {
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switch (eventId) {
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case 1:
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return errorNotifierEvent;
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case 2:
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return unknownEvent;
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default:
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return nullptr;
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}
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}
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}
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@ -1,61 +0,0 @@
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// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#pragma once
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#include "nvdevice.h"
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namespace skyline::service::nvdrv::device {
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/**
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* @brief NvHostCtrlGpu (/dev/nvhost-ctrl-gpu) is used for context independent operations on the underlying GPU
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* @url https://switchbrew.org/wiki/NV_services#.2Fdev.2Fnvhost-ctrl-gpu
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*/
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class NvHostCtrlGpu : public NvDevice {
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private:
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std::shared_ptr<type::KEvent> errorNotifierEvent;
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std::shared_ptr<type::KEvent> unknownEvent;
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public:
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NvHostCtrlGpu(const DeviceState &state);
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/**
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* @brief Returns a u32 GPU ZCULL Context Size
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE
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*/
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NvStatus ZCullGetCtxSize(IoctlType type, span<u8> buffer, span<u8> inlineBuffer);
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/**
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* @brief Returns a the GPU ZCULL Information
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_ZCULL_GET_INFO
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*/
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NvStatus ZCullGetInfo(IoctlType type, span<u8> buffer, span<u8> inlineBuffer);
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/**
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* @brief Returns a struct with certain GPU characteristics
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_GET_CHARACTERISTICS
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*/
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NvStatus GetCharacteristics(IoctlType type, span<u8> buffer, span<u8> inlineBuffer);
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/**
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* @brief Returns the TPC mask value for each GPC
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_GET_TPC_MASKS
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*/
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NvStatus GetTpcMasks(IoctlType type, span<u8> buffer, span<u8> inlineBuffer);
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/**
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* @brief Returns the mask value for a ZBC slot
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* @url https://switchbrew.org/wiki/NV_services#NVGPU_GPU_IOCTL_ZBC_GET_ACTIVE_SLOT_MASK
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*/
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NvStatus GetActiveSlotMask(IoctlType type, span<u8> buffer, span<u8> inlineBuffer);
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std::shared_ptr<type::KEvent> QueryEvent(u32 eventId) override;
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NVDEVICE_DECL(
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NVFUNC(0x4701, NvHostCtrlGpu, ZCullGetCtxSize),
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NVFUNC(0x4702, NvHostCtrlGpu, ZCullGetInfo),
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NVFUNC(0x4706, NvHostCtrlGpu, GetTpcMasks),
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NVFUNC(0x4705, NvHostCtrlGpu, GetCharacteristics),
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NVFUNC(0x4714, NvHostCtrlGpu, GetActiveSlotMask)
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)
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};
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}
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