mirror of
https://github.com/skyline-emu/skyline.git
synced 2024-11-26 21:54:16 +01:00
Rewrite all Maxwell 3D registers up to clears to match Nvidia docs
All the names are directly translated from Nvidia docs, with minimal conversions to enums/structs when appropriate. Not all registers have been rewritten, only those that are needed to implement clears and dynamic state, the rest will be added as they are used in the GPU rework.
This commit is contained in:
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d7eab40f1c
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@ -35,7 +35,7 @@ namespace skyline::gpu {
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.type = vk::DescriptorType::eStorageImage,
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},
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vk::DescriptorPoolSize{
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.descriptorCount = maxwell3d::RenderTargetCount,
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.descriptorCount = maxwell3d::ColorTargetCount,
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.type = vk::DescriptorType::eInputAttachment,
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},
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}; //!< A best approximate ratio of descriptors of each type that may be utilized, the total amount will grow in these ratios
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File diff suppressed because it is too large
Load Diff
@ -5,7 +5,7 @@
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#pragma once
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#include <gpu/interconnect/graphics_context.h>
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#include "maxwell/types.h"
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#include "engine.h"
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#include "inline2memory.h"
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@ -119,22 +119,30 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0xDF, u32> rasterizerEnable;
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Register<0xE0, std::array<type::TransformFeedbackBuffer, type::TransformFeedbackBufferCount>> transformFeedbackBuffers;
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Register<0x1C0, std::array<type::TransformFeedbackBufferState, type::TransformFeedbackBufferCount>> transformFeedbackBufferStates;
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Register<0x1D1, u32> transformFeedbackEnable;
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Register<0xE0, std::array<type::StreamOutBuffer, type::StreamOutBufferCount>> streamOutBuffers;
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Register<0x1C0, std::array<type::TransformFeedbackBufferState, type::StreamOutBufferCount>> transformFeedbackBufferStates;
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Register<0x1D1, u32> streamOutEnable;
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Register<0x200, std::array<type::ColorRenderTarget, type::RenderTargetCount>> renderTargets;
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Register<0x280, std::array<type::ViewportTransform, type::ViewportCount>> viewportTransforms;
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Register<0x300, std::array<type::Viewport, type::ViewportCount>> viewports;
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Register<0x200, std::array<type::ColorTarget, type::ColorTargetCount>> colorTargets;
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Register<0x280, std::array<type::Viewport, type::ViewportCount>> viewports;
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Register<0x300, std::array<type::ViewportClip, type::ViewportCount>> viewportClips;
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Register<0x35D, u32> drawVertexFirst; //!< The first vertex to draw
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Register<0x35E, u32> drawVertexCount; //!< The amount of vertices to draw, calling this method triggers non-indexed drawing
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Register<0x35B, type::ClearRect> clearRect;
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Register<0x35F, type::DepthMode> depthMode;
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Register<0x360, std::array<u32, 4>> clearColorValue;
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Register<0x364, float> clearDepthValue;
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Register<0x368, u32> clearStencilValue;
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Register<0x35D, u32> vertexArrayStart; //!< The first vertex to draw
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struct DrawVertexArray {
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u32 count;
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};
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Register<0x35E, DrawVertexArray> drawVertexArray; //!< The amount of vertices to draw, calling this method triggers non-indexed drawing
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Register<0x35F, type::ZClipRange> zClipRange;
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Register<0x360, std::array<u32, 4>> colorClearValue;
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Register<0x364, float> zClearValue;
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Register<0x368, u32> stencilClearValue;
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struct PolygonMode {
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type::PolygonMode front; // 0x36B
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@ -153,12 +161,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x370, DepthBiasEnable> depthBiasEnable;
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struct StencilBackExtra {
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u32 compareReference; // 0x3D5
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u32 writeMask; // 0x3D6
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u32 compareMask; // 0x3D7
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};
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Register<0x3D5, StencilBackExtra> stencilBackExtra;
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Register<0x3D5, type::BackStencilValues> backStencilValues;
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Register<0x3D8, u32> tiledCacheEnable;
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struct TiledCacheSize {
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@ -167,25 +170,26 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x3D9, TiledCacheSize> tiledCacheSize;
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Register<0x3E4, u32> commonColorWriteMask; //!< If enabled, the color write masks for all RTs must be set to that of the first RT
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Register<0x3E4, u32> singleCtWriteControl; //!< If enabled, the color write masks for all RTs must be set to that of the first RT
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Register<0x3E7, float> depthBoundsNear;
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Register<0x3E8, float> depthBoundsFar;
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Register<0x3E7, float> depthBoundsMin;
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Register<0x3E8, float> depthBoundsMax;
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Register<0x3EB, u32> rtSeparateFragData;
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Register<0x3EB, u32> ctMrtEnable;
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Register<0x3F8, Address> depthTargetAddress;
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Register<0x3FA, type::DepthRtFormat> depthTargetFormat;
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Register<0x3FB, type::RenderTargetTileMode> depthTargetTileMode;
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Register<0x3FC, u32> depthTargetLayerStride;
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Register<0x3F8, Address> ztOffset;
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Register<0x3FA, type::ZtFormat> ztFormat;
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Register<0x3FB, type::ZtBlockSize> ztBlockSize;
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Register<0x3FC, u32> ztArrayPitch;
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Register<0x3FD, type::SurfaceClip> surfaceClip;
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Register<0x458, std::array<type::VertexAttribute, type::VertexAttributeCount>> vertexAttributeState;
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Register<0x43E, type::ClearSurfaceControl> clearSurfaceControl;
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Register<0x487, type::RenderTargetControl> renderTargetControl;
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Register<0x458, std::array<type::VertexAttribute, type::VertexAttributeCount>> vertexAttributes;
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Register<0x48A, u32> depthTargetWidth;
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Register<0x48B, u32> depthTargetHeight;
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Register<0x48C, type::RenderTargetArrayMode> depthTargetArrayMode;
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Register<0x487, type::CtSelect> ctSelect;
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Register<0x48A, type::ZtSize> ztSize;
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Register<0x48D, bool> linkedTscHandle; //!< If enabled, the TSC index in a bindless texture handle is ignored and the TIC index is used as the TSC index, otherwise the TSC index from the bindless texture handle is used
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@ -193,9 +197,9 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x4B9, u32> independentBlendEnable;
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Register<0x4BA, u32> depthWriteEnable;
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Register<0x4BB, u32> alphaTestEnable;
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Register<0x4C3, type::CompareOp> depthTestFunc;
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Register<0x4C3, type::CompareFunc> depthTestFunc;
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Register<0x4C4, float> alphaTestRef;
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Register<0x4C5, type::CompareOp> alphaTestFunc;
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Register<0x4C5, type::CompareFunc> alphaTestFunc;
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Register<0x4C6, u32> drawTFBStride;
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struct BlendConstant {
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@ -204,7 +208,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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float blue; // 0x4C9
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float alpha; // 0x4CA
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};
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Register<0x4C7, std::array<float, type::BlendColorChannelCount>> blendConstant;
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Register<0x4C7, std::array<float, type::BlendColorChannelCount>> blendConsts;
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struct BlendStateCommon {
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u32 seperateAlpha; // 0x4CF
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@ -220,34 +224,20 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x4CF, BlendStateCommon> blendStateCommon;
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Register<0x4D8, std::array<u32, type::RenderTargetCount>> rtBlendEnable;
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Register<0x4D8, std::array<u32, type::ColorTargetCount>> rtBlendEnable;
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Register<0x4E0, u32> stencilEnable;
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struct StencilFront {
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type::StencilOp failOp; // 0x4E1
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type::StencilOp zFailOp; // 0x4E2
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type::StencilOp passOp; // 0x4E3
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type::CompareOp compareOp; // 0x4E4
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u32 compareReference; // 0x4E5
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u32 compareMask; // 0x4E6
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Register<0x4E1, type::StencilOps> stencilOps;
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Register<0x4E5, type::StencilValues> stencilValues;
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u32 writeMask; // 0x4E7
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};
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Register<0x4E1, StencilFront> stencilFront;
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Register<0x4EB, type::WindowOrigin> windowOrigin;
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struct WindowOriginMode {
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bool isOriginLowerLeft : 1;
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u8 _pad_ : 3;
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bool flipFrontFace : 1;
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};
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Register<0x4EB, WindowOriginMode> windowOriginMode;
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Register<0x4EC, float> lineWidthSmooth;
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Register<0x4EC, float> lineWidth;
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Register<0x4ED, float> lineWidthAliased;
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Register<0x50D, i32> drawBaseVertex;
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Register<0x50E, u32> drawBaseInstance;
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Register<0x50D, u32> globalBaseVertexIndex;
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Register<0x50E, u32> globalBaseInstanceIndex;
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Register<0x544, u32> clipDistanceEnable;
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Register<0x545, u32> sampleCounterEnable;
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@ -256,7 +246,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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Register<0x548, u32> pointSpriteEnable;
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Register<0x54A, u32> shaderExceptions;
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Register<0x54D, u32> multisampleEnable;
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Register<0x54E, u32> depthTargetEnable;
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Register<0x54E, type::ZtSelect> ztSelect;
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Register<0x54F, type::MultisampleControl> multisampleControl;
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@ -266,8 +256,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x557, SamplerPool> samplerPool;
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Register<0x55B, float> depthBiasFactor;
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Register<0x55C, u32> lineSmoothEnable;
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Register<0x55B, float> slopeScaleDepthBias;
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Register<0x55C, u32> aliasedLineWidthEnable;
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struct TexturePool {
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Address address; // 0x55D
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@ -275,46 +265,79 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x55D, TexturePool> texturePool;
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Register<0x565, u32> stencilTwoSideEnable; //!< Determines if the back-facing stencil state uses the front facing stencil state or independent stencil state
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Register<0x565, u32> twoSidedStencilTestEnable; //!< Determines if the back-facing stencil state uses the front facing stencil state or independent stencil state
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struct StencilBack {
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type::StencilOp failOp; // 0x566
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type::StencilOp zFailOp; // 0x567
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type::StencilOp passOp; // 0x568
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type::CompareOp compareOp; // 0x569
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};
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Register<0x566, StencilBack> stencilBack;
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Register<0x566, type::StencilOps> stencilBack;
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Register<0x56F, float> depthBiasUnits;
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Register<0x56F, float> depthBias;
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Register<0x581, type::PointCoordReplace> pointCoordReplace;
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Register<0x582, Address> setProgramRegion;
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Register<0x585, u32> vertexEndGl; //!< Method-only register with no real value, used after calling vertexBeginGl to invoke the draw
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Register<0x586, type::VertexBeginGl> vertexBeginGl; //!< Similar to glVertexBegin semantically, supplies a primitive topology for draws alongside instancing data
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Register<0x585, u32> end; //!< Method-only register with no real value, used after calling vertexBeginGl to invoke the draw
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union Begin {
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u32 raw;
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enum class PrimitiveId : u8 {
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First = 0,
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Unchanged = 1,
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};
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enum class InstanceId : u8 {
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First = 0,
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Subsequent = 1,
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Unchanged = 2
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};
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enum class SplitMode : u8 {
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NormalBeginNormalEnd = 0,
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NormalBeginOpenEnd = 1,
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OpenBeginOpenEnd = 2,
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OpenBeginNormalEnd = 3
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};
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struct {
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type::DrawTopology op;
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u16 _pad0_ : 8;
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PrimitiveId primitiveId : 1;
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u8 _pad1_ : 1;
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InstanceId instanceId : 2;
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SplitMode splitMode : 4;
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};
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};
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static_assert(sizeof(Begin) == sizeof(u32));
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Register<0x586, Begin> begin; //!< Similar to glVertexBegin semantically, supplies a primitive topology for draws alongside instancing data
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Register<0x591, u32> primitiveRestartEnable;
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Register<0x592, u32> primitiveRestartIndex;
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Register<0x5A1, u32> provokingVertexIsLast;
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Register<0x5E7, type::ZtLayer> ztLayer;
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Register<0x5F2, type::IndexBuffer> indexBuffer;
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Register<0x5F7, u32> drawIndexFirst; //!< The first element in the index buffer to draw
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Register<0x5F8, u32> drawIndexCount; //!< The amount of elements to draw, calling this method triggers indexed drawing
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struct DrawIndexBuffer {
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u32 count;
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};
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Register<0x5F8, DrawIndexBuffer> drawIndexBuffer;
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Register<0x61F, float> depthBiasClamp;
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Register<0x620, std::array<u32, type::VertexBufferCount>> isVertexInputRatePerInstance; //!< A per-VBO boolean denoting if the vertex input rate should be per vertex or per instance
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Register<0x620, std::array<type::VertexStreamInstance, type::VertexStreamCount>> vertexStreamInstance; //!< A per-VBO boolean denoting if the vertex input rate should be per vertex or per instance
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Register<0x646, u32> cullFaceEnable;
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Register<0x647, type::FrontFace> frontFace;
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Register<0x648, type::CullFace> cullFace;
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Register<0x649, u32> pixelCentreImage;
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Register<0x64B, u32> viewportTransformEnable;
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Register<0x64B, u32> viewportScaleOffsetEnable;
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Register<0x64F, type::ViewVolumeClipControl> viewVolumeClipControl;
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Register<0x652, type::PrimitiveTopologyControl> primitiveTopologyControl;
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Register<0x65C, type::PrimitiveTopology> primitiveTopology;
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Register<0x66F, u32> depthBoundsEnable;
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struct ColorLogicOp {
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@ -323,8 +346,8 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x671, ColorLogicOp> colorLogicOp;
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Register<0x674, type::ClearBuffers> clearBuffers;
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Register<0x680, std::array<type::ColorWriteMask, type::RenderTargetCount>> colorWriteMask;
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Register<0x674, type::ClearSurface> clearSurface;
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Register<0x680, std::array<type::ColorWriteMask, type::ColorTargetCount>> colorWriteMask;
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struct Semaphore {
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Address address; // 0x6C0
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@ -333,19 +356,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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};
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Register<0x6C0, Semaphore> semaphore;
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struct VertexBuffer {
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union {
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u32 raw;
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struct {
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u32 stride : 12;
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u32 enable : 1;
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};
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} config;
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Address iova;
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u32 divisor;
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};
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static_assert(sizeof(VertexBuffer) == sizeof(u32) * 4);
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Register<0x700, std::array<VertexBuffer, type::VertexBufferCount>> vertexBuffers;
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Register<0x700, std::array<type::VertexStream, type::VertexStreamCount>> vertexStreams;
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struct IndependentBlend {
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u32 seperateAlpha;
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@ -357,34 +368,31 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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type::BlendFactor alphaDstFactor;
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u32 _pad_;
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};
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Register<0x780, std::array<IndependentBlend, type::RenderTargetCount>> independentBlend;
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Register<0x780, std::array<IndependentBlend, type::ColorTargetCount>> independentBlend;
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Register<0x7C0, std::array<Address, type::VertexBufferCount>> vertexBufferLimits; //!< A per-VBO IOVA denoting the end of the vertex buffer
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Register<0x7C0, std::array<Address, type::VertexStreamCount>> vertexStreamLimits; //!< A per-VBO IOVA denoting the end of the vertex buffer
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Register<0x800, std::array<type::SetProgramInfo, type::ShaderStageCount>> setProgram;
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Register<0x8C0, u32[0x20]> firmwareCall;
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struct ConstantBufferSelector {
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u32 size;
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Address address;
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};
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Register<0x8E0, ConstantBufferSelector> constantBufferSelector;
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Register<0x8E0, type::ConstantBufferSelector> constantBufferSelector;
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/**
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* @brief Allows updating the currently selected constant buffer inline with an offset and up to 16 words of data
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*/
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struct ConstantBufferUpdate {
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struct LoadConstantBuffer {
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u32 offset;
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std::array<u32, 16> data;
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};
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Register<0x8E3, ConstantBufferUpdate> constantBufferUpdate;
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Register<0x8E3, LoadConstantBuffer> loadConstantBuffer;
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Register<0x900, std::array<type::Bind, type::PipelineStageCount>> bind; //!< Binds constant buffers to pipeline stages
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Register<0x900, std::array<type::BindGroup, type::PipelineStageCount>> bindGroups; //!< Binds constant buffers to pipeline stages
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Register<0x982, u32> bindlessTextureConstantBufferIndex; //!< The index of the constant buffer containing bindless texture descriptors
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Register<0xA00, std::array<u32, (type::TransformFeedbackVaryingCount / sizeof(u32)) * type::TransformFeedbackBufferCount>> transformFeedbackVaryings;
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Register<0xA00, std::array<u32, (type::TransformFeedbackVaryingCount / sizeof(u32)) * type::StreamOutBufferCount>> transformFeedbackVaryings;
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};
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static_assert(sizeof(Registers) == (EngineMethodsEnd * sizeof(u32)));
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#pragma pack(pop)
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