From be2546138d28404c74d893b4c81a0a2e49638f36 Mon Sep 17 00:00:00 2001 From: Billy Laws Date: Fri, 13 May 2022 22:19:59 +0100 Subject: [PATCH] Move IOVA class to GMMU so it can be used for other engines --- .../gpu/interconnect/graphics_context.h | 18 +----------------- app/src/main/cpp/skyline/soc/gm20b/gmmu.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/app/src/main/cpp/skyline/gpu/interconnect/graphics_context.h b/app/src/main/cpp/skyline/gpu/interconnect/graphics_context.h index 5db0fbbe..06017803 100644 --- a/app/src/main/cpp/skyline/gpu/interconnect/graphics_context.h +++ b/app/src/main/cpp/skyline/gpu/interconnect/graphics_context.h @@ -18,6 +18,7 @@ #include "conversion/quads.h" namespace skyline::gpu::interconnect { + using IOVA = soc::gm20b::IOVA; namespace maxwell3d = soc::gm20b::engine::maxwell3d::type; namespace ShaderCompiler = ::Shader; //!< Namespace alias to avoid conflict with the `Shader` class @@ -31,23 +32,6 @@ namespace skyline::gpu::interconnect { soc::gm20b::ChannelContext &channelCtx; gpu::interconnect::CommandExecutor &executor; - /** - * @brief A host IOVA address composed of 32-bit low/high register values - * @note This differs from maxwell3d::Address in that it is little-endian rather than big-endian ordered for the register values - */ - union IOVA { - u64 iova; - struct { - u32 low; - u32 high; - }; - - operator u64 &() { - return iova; - } - }; - static_assert(sizeof(IOVA) == sizeof(u64)); - public: GraphicsContext(GPU &gpu, soc::gm20b::ChannelContext &channelCtx, gpu::interconnect::CommandExecutor &executor) : gpu(gpu), channelCtx(channelCtx), executor(executor) { scissors.fill(DefaultScissor); diff --git a/app/src/main/cpp/skyline/soc/gm20b/gmmu.h b/app/src/main/cpp/skyline/soc/gm20b/gmmu.h index 9eb3cadd..8e874398 100644 --- a/app/src/main/cpp/skyline/soc/gm20b/gmmu.h +++ b/app/src/main/cpp/skyline/soc/gm20b/gmmu.h @@ -18,4 +18,21 @@ namespace skyline::soc::gm20b { struct AddressSpaceContext { GMMU gmmu; }; + + /** + * @brief A host IOVA address composed of 32-bit low/high register values + * @note This differs from engine::Address in that it is little-endian rather than big-endian ordered for the register values + */ + union IOVA { + u64 iova; + struct { + u32 low; + u32 high; + }; + + operator u64 &() { + return iova; + } + }; + static_assert(sizeof(IOVA) == sizeof(u64)); }