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Commonise maxwell3d texture code

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This will be shared with the compute engine implementation.
This commit is contained in:
Billy Laws 2022-11-18 21:13:49 +00:00
parent 61e95c4b2c
commit be8cbabd97
10 changed files with 23 additions and 29 deletions
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2
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/textures.cpp → app/src/main/cpp/skyline/gpu/interconnect/common/textures.cpp
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@ -7,7 +7,7 @@
#include <gpu/texture/format.h>
#include "textures.h"
namespace skyline::gpu::interconnect::maxwell3d {
namespace skyline::gpu::interconnect {
void TexturePoolState::EngineRegisters::DirtyBind(DirtyManager &manager, dirty::Handle handle) const {
manager.Bind(handle, texHeaderPool);
}

7
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/textures.h → app/src/main/cpp/skyline/gpu/interconnect/common/textures.h
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@ -4,15 +4,16 @@
#pragma once
#include <tsl/robin_map.h>
#include <shader_compiler/runtime_info.h>
#include <shader_compiler/shader_info.h>
#include <gpu/texture/texture.h>
#include "common.h"
#include "tic.h"
namespace skyline::gpu::interconnect::maxwell3d {
namespace skyline::gpu::interconnect {
class TexturePoolState : dirty::CachedManualDirty {
public:
struct EngineRegisters {
const engine::TexHeaderPool &texHeaderPool;
const engine_common::TexHeaderPool &texHeaderPool;
void DirtyBind(DirtyManager &manager, dirty::Handle handle) const;
};

0
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/tic.h → app/src/main/cpp/skyline/gpu/interconnect/common/tic.h
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2
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/maxwell_3d.h
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@ -5,10 +5,10 @@
#include <gpu/descriptor_allocator.h>
#include <gpu/interconnect/common/samplers.h>
#include <gpu/interconnect/common/textures.h>
#include "common.h"
#include "active_state.h"
#include "constant_buffers.h"
#include "textures.h"
namespace skyline::gpu::interconnect::maxwell3d {
/**

2
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/pipeline_manager.h
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@ -7,10 +7,10 @@
#include <shader_compiler/frontend/ir/program.h>
#include <gpu/cache/graphics_pipeline_cache.h>
#include <gpu/interconnect/common/samplers.h>
#include <gpu/interconnect/common/textures.h>
#include "common.h"
#include "packed_pipeline_state.h"
#include "constant_buffers.h"
#include "textures.h"
namespace skyline::gpu {
class TextureView;

2
app/src/main/cpp/skyline/gpu/interconnect/maxwell_3d/pipeline_state.h
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@ -285,7 +285,7 @@ namespace skyline::gpu::interconnect::maxwell3d {
public:
struct EngineRegisters {
const std::array<u32, 8> &postVtgShaderAttributeSkipMask;
const engine::BindlessTexture &bindlessTexture;
const engine_common::BindlessTexture &bindlessTexture;
const u32 &apiMandatedEarlyZ;
void DirtyBind(DirtyManager &manager, dirty::Handle handle) const;

12
app/src/main/cpp/skyline/soc/gm20b/engines/engine.h
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@ -53,6 +53,18 @@ namespace skyline::soc::gm20b::engine {
};
static_assert(sizeof(TexSamplerPool) == sizeof(u32) * 3);
struct TexHeaderPool {
Address offset;
u32 maximumIndex;
};
static_assert(sizeof(TexHeaderPool) == sizeof(u32) * 3);
struct BindlessTexture {
u8 constantBufferSlotSelect : 5;
u32 _pad0_ : 27;
};
static_assert(sizeof(BindlessTexture) == sizeof(u32));
constexpr u32 EngineMethodsEnd{0xE00}; //!< All methods above this are passed to the MME on supported engines
/**

9
app/src/main/cpp/skyline/soc/gm20b/engines/kepler_compute.h
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@ -96,8 +96,7 @@ namespace skyline::soc::gm20b::engine {
Register<0x54A, u32> shaderExceptions;
Register<0x557, TexSamplerPool> texSamplerPool;
Register<0x55D, Address> texHeaderPool;
Register<0x55F, u32> texHeaderPoolMaximumIndex;
Register<0x55D, TexHeaderPool> texHeaderPool;
Register<0x582, Address> programRegion;
@ -149,12 +148,6 @@ namespace skyline::soc::gm20b::engine {
Register<0x6C0, ReportSemaphore> reportSemaphore;
struct BindlessTexture {
u8 constantBufferSlotSelect : 3;
u32 _pad_ : 29;
};
static_assert(sizeof(BindlessTexture) == 0x4);
Register<0x982, BindlessTexture> bindlessTexture;
} registers{};
static_assert(sizeof(Registers) == (EngineMethodsEnd * 0x4));

12
app/src/main/cpp/skyline/soc/gm20b/engines/maxwell/types.h
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@ -556,12 +556,6 @@ namespace skyline::soc::gm20b::engine::maxwell3d::type {
};
static_assert(sizeof(SamplerBinding) == sizeof(u32));
struct TexHeaderPool {
Address offset;
u32 maximumIndex;
};
static_assert(sizeof(TexHeaderPool) == sizeof(u32) * 3);
enum class CompareFunc : u32 {
D3DNever = 1,
D3DLess = 2,
@ -874,12 +868,6 @@ namespace skyline::soc::gm20b::engine::maxwell3d::type {
};
static_assert(sizeof(BindGroup) == (sizeof(u32) * 8));
struct BindlessTexture {
u8 constantBufferSlotSelect : 5;
u32 _pad0_ : 27;
};
static_assert(sizeof(BindlessTexture) == sizeof(u32));
constexpr static size_t ShaderStageConstantBufferCount{18}; //!< Maximum amount of constant buffers that can be bound to a single pipeline stage
constexpr static size_t PipelineCount{6}; //!< Amount of shader stages on Maxwell 3D

4
app/src/main/cpp/skyline/soc/gm20b/engines/maxwell_3d.h
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@ -271,7 +271,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
Register<0x55B, float> slopeScaleDepthBias;
Register<0x55C, u32> aliasedLineWidthEnable;
Register<0x55D, type::TexHeaderPool> texHeaderPool;
Register<0x55D, TexHeaderPool> texHeaderPool;
Register<0x565, u32> twoSidedStencilTestEnable; //!< Determines if the back-facing stencil state uses the front facing stencil state or independent stencil state
@ -414,7 +414,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
Register<0x900, std::array<type::BindGroup, type::ShaderStageCount>> bindGroups; //!< Binds constant buffers to pipeline stages
Register<0x982, type::BindlessTexture> bindlessTexture; //!< The index of the constant buffer containing bindless texture descriptors
Register<0x982, BindlessTexture> bindlessTexture; //!< The index of the constant buffer containing bindless texture descriptors
Register<0xA00, std::array<std::array<u8, type::StreamOutLayoutSelectAttributeCount>, type::StreamOutBufferCount>> streamOutLayoutSelect;
};