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https://github.com/skyline-emu/skyline.git
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Use NCE memory tracking for guest shaders
Prevents needing to hash them for every single pipeline state update, without this just hashing shaders takes up a significant amount of time.
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@ -8,6 +8,10 @@
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#include <soc/gm20b/engines/maxwell/types.h>
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#include <gpu/buffer.h>
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namespace skyline::kernel {
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class MemoryManager;
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}
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namespace skyline::soc::gm20b {
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struct ChannelContext;
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}
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@ -26,6 +30,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
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soc::gm20b::ChannelContext &channelCtx;
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CommandExecutor &executor;
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GPU &gpu;
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nce::NCE &nce;
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kernel::MemoryManager &memory;
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};
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/**
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@ -14,9 +14,11 @@ namespace skyline::gpu::interconnect::maxwell3d {
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Maxwell3D::Maxwell3D(GPU &gpu,
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soc::gm20b::ChannelContext &channelCtx,
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gpu::interconnect::CommandExecutor &executor,
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nce::NCE &nce,
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skyline::kernel::MemoryManager &memoryManager,
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DirtyManager &manager,
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const EngineRegisterBundle ®isterBundle)
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: ctx{channelCtx, executor, gpu},
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: ctx{channelCtx, executor, gpu, nce, memoryManager},
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activeState{manager, registerBundle.activeStateRegisters},
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clearEngineRegisters{registerBundle.clearRegisters},
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constantBuffers{manager, registerBundle.constantBufferSelectorRegisters},
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@ -47,6 +47,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
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Maxwell3D(GPU &gpu,
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soc::gm20b::ChannelContext &channelCtx,
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gpu::interconnect::CommandExecutor &executor,
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nce::NCE &nce,
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kernel::MemoryManager &memoryManager,
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DirtyManager &manager,
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const EngineRegisterBundle ®isterBundle);
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@ -4,6 +4,8 @@
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// Copyright © 2022 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <range/v3/algorithm/for_each.hpp>
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#include <nce.h>
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#include <kernel/memory.h>
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#include <soc/gm20b/channel.h>
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#include <soc/gm20b/gmmu.h>
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#include <gpu/texture/format.h>
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@ -228,24 +230,74 @@ namespace skyline::gpu::interconnect::maxwell3d {
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return;
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}
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binary.binary = ctx.channelCtx.asCtx->gmmu.ReadTill(shaderBacking, engine->programRegion + engine->pipeline.programOffset, [](span<u8> data) -> std::optional<size_t> {
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auto [blockMapping, blockOffset]{ctx.channelCtx.asCtx->gmmu.LookupBlock(engine->programRegion + engine->pipeline.programOffset)};
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// Skip looking up the mirror if it is the same as the one used for the previous update
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if (!mirrorBlock.valid() || !mirrorBlock.contains(blockMapping)) {
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auto mirrorIt{mirrorMap.find(blockMapping.data())};
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if (mirrorIt == mirrorMap.end()) {
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// Allocate a host mirror for the mapping and trap the guest region
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auto newIt{mirrorMap.emplace(blockMapping.data(), std::make_unique<MirrorEntry>(ctx.memory.CreateMirror(blockMapping)))};
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// We need to create the trap after allocating the entry so that we have an `invalid` pointer we can pass in
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auto trapHandle{ctx.nce.CreateTrap(blockMapping, [](){}, [](){ return true; }, [dirty = &newIt.first->second->dirty, mutex = &trapMutex](){
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std::scoped_lock lock{*mutex}; // Don't use lock callback here since we need trapMutex to be always locked on accesses to prevent UAFs
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*dirty = true;
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return true;
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})};
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// Write only trap
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ctx.nce.TrapRegions(trapHandle, true);
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entry = newIt.first->second.get();
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entry->trap = trapHandle;
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} else {
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entry = mirrorIt->second.get();
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}
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mirrorBlock = blockMapping;
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}
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// If the mirror entry has been written to, clear its shader binary cache and retrap to catch any future writes
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if (entry->dirty) {
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entry->cache.clear();
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entry->dirty = false;
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ctx.nce.TrapRegions(*entry->trap, true);
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} else if (auto it{entry->cache.find(blockMapping.data() + blockOffset)}; it != entry->cache.end()) {
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binary = it->second.binary;
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hash = it->second.hash;
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return;
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}
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// If nothing was in the cache then do a full shader parse
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auto guest{[](span<u8> mapping) {
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// We attempt to find the shader size by looking for "BRA $" (Infinite Loop) which is used as padding at the end of the shader
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// UAM Shader Compiler Reference: https://github.com/devkitPro/uam/blob/5a5afc2bae8b55409ab36ba45be63fcb73f68993/source/compiler_iface.cpp#L319-L351
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constexpr u64 BraSelf1{0xE2400FFFFF87000F}, BraSelf2{0xE2400FFFFF07000F};
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span<u64> shaderInstructions{data.cast<u64, std::dynamic_extent, true>()};
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span<u64> shaderInstructions{mapping.cast<u64, std::dynamic_extent, true>()};
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for (auto it{shaderInstructions.begin()}; it != shaderInstructions.end(); it++) {
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auto instruction{*it};
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if (instruction == BraSelf1 || instruction == BraSelf2) [[unlikely]]
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// It is far more likely that the instruction doesn't match so this is an unlikely case
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return static_cast<size_t>(std::distance(shaderInstructions.begin(), it)) * sizeof(u64);
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return span{shaderInstructions.begin(), it}.cast<u8>();
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}
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return std::nullopt;
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});
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return span<u8>{};
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}(blockMapping.subspan(blockOffset))};
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binary.baseOffset = engine->pipeline.programOffset;
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hash = XXH64(guest.data(), guest.size_bytes(), 0);
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hash = XXH64(binary.binary.data(), binary.binary.size_bytes(), 0);
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binary.binary = {guest.data() - mirrorBlock.data() + entry->mirror.data(), guest.size()};
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entry->cache.insert({blockMapping.data() + blockOffset, CacheEntry{binary, hash}});
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}
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PipelineStageState::~PipelineStageState() {
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std::scoped_lock lock{trapMutex};
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//for (const auto &mirror : mirrorMap)
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// ctx.nce.DestroyTrap(*mirror.second->trap);
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}
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/* Vertex Input State */
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@ -65,12 +65,31 @@ namespace skyline::gpu::interconnect::maxwell3d {
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};
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private:
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struct CacheEntry {
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ShaderBinary binary;
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u64 hash;
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CacheEntry(ShaderBinary binary, u64 hash) : binary{binary}, hash{hash} {}
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};
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/**
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* @brief Holds mirror state for a single GPU mapped block
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*/
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struct MirrorEntry {
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span<u8> mirror;
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tsl::robin_map<u8 *, CacheEntry> cache;
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std::optional<nce::NCE::TrapHandle> trap;
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bool dirty{};
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MirrorEntry(span<u8> alignedMirror) : mirror{alignedMirror} {}
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};
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dirty::BoundSubresource<EngineRegisters> engine;
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engine::Pipeline::Shader::Type shaderType;
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constexpr static size_t MaxShaderBytecodeSize{1 * 1024 * 1024}; //!< The largest shader binary that we support (1 MiB)
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std::array<u8, MaxShaderBytecodeSize> shaderBacking;
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tsl::robin_map<u8 *, std::unique_ptr<MirrorEntry>> mirrorMap;
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std::mutex trapMutex; //!< Protects accesses from trap handlers to the mirror map
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MirrorEntry *entry{};
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span<u8> mirrorBlock{}; //!< Guest mapped memory block corresponding to `entry`
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public:
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ShaderBinary binary;
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@ -78,6 +97,8 @@ namespace skyline::gpu::interconnect::maxwell3d {
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PipelineStageState(dirty::Handle dirtyHandle, DirtyManager &manager, const EngineRegisters &engine, u8 shaderType);
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~PipelineStageState();
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void Flush(InterconnectContext &ctx);
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};
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@ -62,7 +62,7 @@ namespace skyline::soc::gm20b::engine::maxwell3d {
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syncpoints{state.soc->host1x.syncpoints},
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i2m{channelCtx},
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dirtyManager{registers},
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interconnect{*state.gpu, channelCtx, executor, dirtyManager, MakeEngineRegisters(registers)},
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interconnect{*state.gpu, channelCtx, executor, *state.nce, state.process->memory, dirtyManager, MakeEngineRegisters(registers)},
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channelCtx{channelCtx} {
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executor.AddFlushCallback([this]() { FlushEngineState(); });
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InitializeRegisters();
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