150 lines
6.0 KiB
C++
150 lines
6.0 KiB
C++
// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <kernel/types/KProcess.h>
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#include "nvhost_ctrl_gpu.h"
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namespace skyline::service::nvdrv::device {
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NvHostCtrlGpu::NvHostCtrlGpu(const DeviceState &state) : NvDevice(state, NvDeviceType::nvhost_ctrl_gpu, {
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{0x80044701, NFUNC(NvHostCtrlGpu::ZCullGetCtxSize)},
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{0x80284702, NFUNC(NvHostCtrlGpu::ZCullGetInfo)},
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{0xC0184706, NFUNC(NvHostCtrlGpu::GetTpcMasks)},
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{0xC0B04705, NFUNC(NvHostCtrlGpu::GetCharacteristics)},
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{0x80084714, NFUNC(NvHostCtrlGpu::GetActiveSlotMask)}
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}) {}
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void NvHostCtrlGpu::ZCullGetCtxSize(IoctlData &buffer) {
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u32 size = 0x1;
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state.process->WriteMemory(size, buffer.output[0].address);
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}
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void NvHostCtrlGpu::ZCullGetInfo(IoctlData &buffer) {
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struct {
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u32 widthAlignPixels{0x20};
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u32 heightAlignPixels{0x20};
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u32 pixelSquaresByAliquots{0x400};
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u32 aliquotTotal{0x800};
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u32 regionByteMultiplier{0x20};
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u32 regionHeaderSize{0x20};
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u32 subregionHeaderSize{0xC0};
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u32 subregionWidthAlignPixels{0x20};
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u32 subregionHeightAlignPixels{0x40};
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u32 subregionCount{0x10};
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} zCullInfo;
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state.process->WriteMemory(zCullInfo, buffer.output[0].address);
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}
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void NvHostCtrlGpu::GetCharacteristics(IoctlData &buffer) {
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struct GpuCharacteristics {
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u32 arch; // 0x120 (NVGPU_GPU_ARCH_GM200)
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u32 impl; // 0xB (NVGPU_GPU_IMPL_GM20B) or 0xE (NVGPU_GPU_IMPL_GM20B_B)
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u32 rev; // 0xA1 (Revision A1)
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u32 numGpc; // 0x1
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u64 l2CacheSize; // 0x40000
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u64 onBoardVideoMemorySize; // 0x0 (not used)
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u32 numTpcPerGpc; // 0x2
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u32 busType; // 0x20 (NVGPU_GPU_BUS_TYPE_AXI)
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u32 bigPageSize; // 0x20000
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u32 compressionPageSize; // 0x20000
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u32 pdeCoverageBitCount; // 0x1B
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u32 availableBigPageSizes; // 0x30000
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u32 gpcMask; // 0x1
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u32 smArchSmVersion; // 0x503 (Maxwell Generation 5.0.3)
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u32 smArchSpaVersion; // 0x503 (Maxwell Generation 5.0.3)
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u32 smArchWarpCount; // 0x80
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u32 gpuVaBitCount; // 0x28
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u32 reserved; // NULL
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u64 flags; // 0x55 (HAS_SYNCPOINTS | SUPPORT_SPARSE_ALLOCS | SUPPORT_CYCLE_STATS | SUPPORT_CYCLE_STATS_SNAPSHOT)
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u32 twodClass; // 0x902D (FERMI_TWOD_A)
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u32 threedClass; // 0xB197 (MAXWELL_B)
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u32 computeClass; // 0xB1C0 (MAXWELL_COMPUTE_B)
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u32 gpfifoClass; // 0xB06F (MAXWELL_CHANNEL_GPFIFO_A)
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u32 inlineToMemoryClass; // 0xA140 (KEPLER_INLINE_TO_MEMORY_B)
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u32 dmaCopyClass; // 0xB0B5 (MAXWELL_DMA_COPY_A)
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u32 maxFbpsCount; // 0x1
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u32 fbpEnMask; // 0x0 (disabled)
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u32 maxLtcPerFbp; // 0x2
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u32 maxLtsPerLtc; // 0x1
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u32 maxTexPerTpc; // 0x0 (not supported)
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u32 maxGpcCount; // 0x1
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u32 ropL2EnMask0; // 0x21D70 (fuse_status_opt_rop_l2_fbp_r)
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u32 ropL2EnMask1; // 0x0
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u64 chipName; // 0x6230326D67 ("gm20b")
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u64 grCompbitStoreBaseHw; // 0x0 (not supported)
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};
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struct Data {
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u64 gpuCharacteristicsBufSize; // InOut
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u64 gpuCharacteristicsBufAddr; // In
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GpuCharacteristics gpuCharacteristics; // Out
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} data = state.process->GetObject<Data>(buffer.input[0].address);
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data.gpuCharacteristics = {
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.arch = 0x120,
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.impl = 0xB,
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.rev = 0xA1,
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.numGpc = 0x1,
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.l2CacheSize = 0x40000,
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.onBoardVideoMemorySize = 0x0,
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.numTpcPerGpc = 0x2,
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.busType = 0x20,
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.bigPageSize = 0x20000,
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.compressionPageSize = 0x20000,
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.pdeCoverageBitCount = 0x1B,
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.availableBigPageSizes = 0x30000,
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.gpcMask = 0x1,
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.smArchSmVersion = 0x503,
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.smArchSpaVersion = 0x503,
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.smArchWarpCount = 0x80,
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.gpuVaBitCount = 0x2,
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.flags = 0x55,
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.twodClass = 0x902D,
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.threedClass = 0xB197,
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.computeClass = 0xB1C0,
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.gpfifoClass = 0xB06F,
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.inlineToMemoryClass = 0xA140,
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.dmaCopyClass = 0xB0B5,
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.maxFbpsCount = 0x1,
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.fbpEnMask = 0x0,
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.maxLtcPerFbp = 0x2,
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.maxLtsPerLtc = 0x1,
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.maxTexPerTpc = 0x0,
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.maxGpcCount = 0x1,
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.ropL2EnMask0 = 0x21D70,
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.ropL2EnMask1 = 0x0,
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.chipName = 0x6230326D67,
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.grCompbitStoreBaseHw = 0x0
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};
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data.gpuCharacteristicsBufSize = 0xA0;
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state.process->WriteMemory(data, buffer.output[0].address);
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}
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void NvHostCtrlGpu::GetTpcMasks(IoctlData &buffer) {
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struct Data {
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u32 maskBufSize; // In
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u32 reserved[3]; // In
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u64 maskBuf; // Out
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} data = state.process->GetObject<Data>(buffer.input[0].address);
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if (data.maskBufSize)
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data.maskBuf = 0x3;
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state.process->WriteMemory(data, buffer.output[0].address);
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}
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void NvHostCtrlGpu::GetActiveSlotMask(IoctlData &buffer) {
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struct Data {
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u32 slot; // Out
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u32 mask; // Out
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} data = {
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.slot = 0x07,
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.mask = 0x01
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};
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state.process->WriteMemory(data, buffer.output[0].address);
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}
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}
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