230 lines
5.1 KiB
C
230 lines
5.1 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015-2017 */
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/* This file is released under LGPL2.
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See COPYING.LGPL2 in root directory for more details
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*/
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#ifndef UNICORN_MIPS_H
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#define UNICORN_MIPS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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// GCC MIPS toolchain has a default macro called "mips" which breaks
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// compilation
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#undef mips
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#ifdef _MSC_VER
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#pragma warning(disable:4201)
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#endif
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//> MIPS registers
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typedef enum UC_MIPS_REG {
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UC_MIPS_REG_INVALID = 0,
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//> General purpose registers
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UC_MIPS_REG_PC,
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UC_MIPS_REG_0,
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UC_MIPS_REG_1,
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UC_MIPS_REG_2,
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UC_MIPS_REG_3,
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UC_MIPS_REG_4,
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UC_MIPS_REG_5,
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UC_MIPS_REG_6,
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UC_MIPS_REG_7,
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UC_MIPS_REG_8,
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UC_MIPS_REG_9,
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UC_MIPS_REG_10,
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UC_MIPS_REG_11,
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UC_MIPS_REG_12,
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UC_MIPS_REG_13,
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UC_MIPS_REG_14,
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UC_MIPS_REG_15,
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UC_MIPS_REG_16,
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UC_MIPS_REG_17,
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UC_MIPS_REG_18,
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UC_MIPS_REG_19,
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UC_MIPS_REG_20,
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UC_MIPS_REG_21,
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UC_MIPS_REG_22,
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UC_MIPS_REG_23,
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UC_MIPS_REG_24,
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UC_MIPS_REG_25,
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UC_MIPS_REG_26,
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UC_MIPS_REG_27,
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UC_MIPS_REG_28,
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UC_MIPS_REG_29,
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UC_MIPS_REG_30,
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UC_MIPS_REG_31,
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//> DSP registers
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UC_MIPS_REG_DSPCCOND,
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UC_MIPS_REG_DSPCARRY,
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UC_MIPS_REG_DSPEFI,
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UC_MIPS_REG_DSPOUTFLAG,
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UC_MIPS_REG_DSPOUTFLAG16_19,
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UC_MIPS_REG_DSPOUTFLAG20,
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UC_MIPS_REG_DSPOUTFLAG21,
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UC_MIPS_REG_DSPOUTFLAG22,
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UC_MIPS_REG_DSPOUTFLAG23,
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UC_MIPS_REG_DSPPOS,
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UC_MIPS_REG_DSPSCOUNT,
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//> ACC registers
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UC_MIPS_REG_AC0,
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UC_MIPS_REG_AC1,
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UC_MIPS_REG_AC2,
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UC_MIPS_REG_AC3,
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//> COP registers
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UC_MIPS_REG_CC0,
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UC_MIPS_REG_CC1,
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UC_MIPS_REG_CC2,
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UC_MIPS_REG_CC3,
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UC_MIPS_REG_CC4,
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UC_MIPS_REG_CC5,
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UC_MIPS_REG_CC6,
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UC_MIPS_REG_CC7,
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//> FPU registers
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UC_MIPS_REG_F0,
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UC_MIPS_REG_F1,
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UC_MIPS_REG_F2,
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UC_MIPS_REG_F3,
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UC_MIPS_REG_F4,
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UC_MIPS_REG_F5,
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UC_MIPS_REG_F6,
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UC_MIPS_REG_F7,
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UC_MIPS_REG_F8,
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UC_MIPS_REG_F9,
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UC_MIPS_REG_F10,
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UC_MIPS_REG_F11,
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UC_MIPS_REG_F12,
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UC_MIPS_REG_F13,
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UC_MIPS_REG_F14,
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UC_MIPS_REG_F15,
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UC_MIPS_REG_F16,
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UC_MIPS_REG_F17,
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UC_MIPS_REG_F18,
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UC_MIPS_REG_F19,
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UC_MIPS_REG_F20,
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UC_MIPS_REG_F21,
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UC_MIPS_REG_F22,
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UC_MIPS_REG_F23,
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UC_MIPS_REG_F24,
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UC_MIPS_REG_F25,
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UC_MIPS_REG_F26,
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UC_MIPS_REG_F27,
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UC_MIPS_REG_F28,
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UC_MIPS_REG_F29,
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UC_MIPS_REG_F30,
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UC_MIPS_REG_F31,
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UC_MIPS_REG_FCC0,
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UC_MIPS_REG_FCC1,
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UC_MIPS_REG_FCC2,
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UC_MIPS_REG_FCC3,
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UC_MIPS_REG_FCC4,
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UC_MIPS_REG_FCC5,
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UC_MIPS_REG_FCC6,
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UC_MIPS_REG_FCC7,
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//> AFPR128
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UC_MIPS_REG_W0,
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UC_MIPS_REG_W1,
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UC_MIPS_REG_W2,
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UC_MIPS_REG_W3,
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UC_MIPS_REG_W4,
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UC_MIPS_REG_W5,
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UC_MIPS_REG_W6,
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UC_MIPS_REG_W7,
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UC_MIPS_REG_W8,
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UC_MIPS_REG_W9,
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UC_MIPS_REG_W10,
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UC_MIPS_REG_W11,
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UC_MIPS_REG_W12,
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UC_MIPS_REG_W13,
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UC_MIPS_REG_W14,
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UC_MIPS_REG_W15,
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UC_MIPS_REG_W16,
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UC_MIPS_REG_W17,
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UC_MIPS_REG_W18,
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UC_MIPS_REG_W19,
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UC_MIPS_REG_W20,
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UC_MIPS_REG_W21,
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UC_MIPS_REG_W22,
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UC_MIPS_REG_W23,
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UC_MIPS_REG_W24,
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UC_MIPS_REG_W25,
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UC_MIPS_REG_W26,
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UC_MIPS_REG_W27,
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UC_MIPS_REG_W28,
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UC_MIPS_REG_W29,
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UC_MIPS_REG_W30,
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UC_MIPS_REG_W31,
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UC_MIPS_REG_HI,
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UC_MIPS_REG_LO,
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UC_MIPS_REG_P0,
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UC_MIPS_REG_P1,
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UC_MIPS_REG_P2,
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UC_MIPS_REG_MPL0,
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UC_MIPS_REG_MPL1,
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UC_MIPS_REG_MPL2,
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UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
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// alias registers
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UC_MIPS_REG_ZERO = UC_MIPS_REG_0,
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UC_MIPS_REG_AT = UC_MIPS_REG_1,
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UC_MIPS_REG_V0 = UC_MIPS_REG_2,
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UC_MIPS_REG_V1 = UC_MIPS_REG_3,
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UC_MIPS_REG_A0 = UC_MIPS_REG_4,
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UC_MIPS_REG_A1 = UC_MIPS_REG_5,
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UC_MIPS_REG_A2 = UC_MIPS_REG_6,
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UC_MIPS_REG_A3 = UC_MIPS_REG_7,
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UC_MIPS_REG_T0 = UC_MIPS_REG_8,
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UC_MIPS_REG_T1 = UC_MIPS_REG_9,
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UC_MIPS_REG_T2 = UC_MIPS_REG_10,
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UC_MIPS_REG_T3 = UC_MIPS_REG_11,
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UC_MIPS_REG_T4 = UC_MIPS_REG_12,
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UC_MIPS_REG_T5 = UC_MIPS_REG_13,
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UC_MIPS_REG_T6 = UC_MIPS_REG_14,
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UC_MIPS_REG_T7 = UC_MIPS_REG_15,
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UC_MIPS_REG_S0 = UC_MIPS_REG_16,
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UC_MIPS_REG_S1 = UC_MIPS_REG_17,
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UC_MIPS_REG_S2 = UC_MIPS_REG_18,
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UC_MIPS_REG_S3 = UC_MIPS_REG_19,
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UC_MIPS_REG_S4 = UC_MIPS_REG_20,
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UC_MIPS_REG_S5 = UC_MIPS_REG_21,
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UC_MIPS_REG_S6 = UC_MIPS_REG_22,
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UC_MIPS_REG_S7 = UC_MIPS_REG_23,
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UC_MIPS_REG_T8 = UC_MIPS_REG_24,
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UC_MIPS_REG_T9 = UC_MIPS_REG_25,
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UC_MIPS_REG_K0 = UC_MIPS_REG_26,
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UC_MIPS_REG_K1 = UC_MIPS_REG_27,
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UC_MIPS_REG_GP = UC_MIPS_REG_28,
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UC_MIPS_REG_SP = UC_MIPS_REG_29,
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UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30,
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UC_MIPS_REG_RA = UC_MIPS_REG_31,
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UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0,
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UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1,
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UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2,
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UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3,
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UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0,
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UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1,
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UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2,
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UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3,
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} UC_MIPS_REG;
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#ifdef __cplusplus
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}
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#endif
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#endif
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