mirror of
https://github.com/skyline-emu/skyline.git
synced 2024-06-11 13:08:47 +02:00
5e8cdfda92
Avoids breaking VK spec in BOTW, as it has the same colour attachment bound twice, but the former is masked out entirely.
1167 lines
33 KiB
C++
1167 lines
33 KiB
C++
// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2021 Skyline Team and Contributors (https://github.com/skyline-emu/)
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// Copyright © 2018-2020 fincs (https://github.com/devkitPro/deko3d)
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#pragma once
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#include <common.h>
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#include <common/macros.h>
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#include <soc/gm20b/engines/engine.h>
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namespace skyline::soc::gm20b::engine::maxwell3d::type {
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#pragma pack(push, 1)
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enum class MmeShadowRamControl : u32 {
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MethodTrack = 0, //!< Tracks all writes to registers in shadow RAM
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MethodTrackWithFilter = 1, //!< Tracks all writes to registers in shadow RAM with a filter
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MethodPassthrough = 2, //!< Does nothing, no write tracking or hooking
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MethodReplay = 3, //!< Replays older tracked writes for any new writes to registers, discarding the contents of the new write
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};
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struct SyncpointAction {
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u16 id : 12;
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u8 _pad0_ : 4;
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bool flushCache : 1;
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u8 _pad1_ : 3;
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bool increment : 1;
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u16 _pad2_ : 11;
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};
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static_assert(sizeof(SyncpointAction) == sizeof(u32));
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/**
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* @brief The input primitive for a tessellated surface
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*/
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enum class TessellationPrimitive : u8 {
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Isoline = 0,
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Triangle = 1,
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Quad = 2,
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};
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/**
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* @brief The spacing between tessellated vertices during primitive generation
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*/
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enum class TessellationSpacing : u8 {
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Equal = 0,
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FractionalOdd = 1,
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FractionalEven = 2,
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};
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/**
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* @brief The winding order and connectivity of tessellated primitives during primitive generation
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*/
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enum class TessellationWinding : u8 {
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CounterClockwiseAndNotConnected = 0, //!< Counter-clockwise, not connected
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ConnectedIsoline = 1, //!< Counter-clockwise, connected (Only for Isolines)
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ClockwiseTriangle = 1, //<! Clockwise, not connected (Only for Triangles)
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ConnectedTriangle = 2, //!< Counter-clockwise, connected (Only for Triangles)
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ClockwiseConnectedTriangle = 3, //!< Clockwise, connected (Only for Triangles)
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};
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constexpr static size_t ColorTargetCount{8}; //!< Maximum amount of render targets that can be bound at once on Maxwell 3D
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struct TargetMemory {
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enum class Layout : u8 {
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BlockLinear = 0,
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Pitch = 1
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};
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enum class ThirdDimensionControl : u8 {
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ThirdDimensionDefinesArraySize = 0,
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ThirdDimensionDefinesDepthSize = 1
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};
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u8 blockWidthLog2 : 4; //!< The width of a block in GOBs with log2 encoding, this is always assumed to be 1 as it is the only configuration the X1 supports
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u8 blockHeightLog2 : 4; //!< The height of a block in GOBs with log2 encoding
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u8 blockDepthLog2 : 4; //!< The depth of a block in GOBs with log2 encoding
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Layout layout : 1;
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u8 _pad0_ : 3;
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ThirdDimensionControl thirdDimensionControl : 1;
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u16 _pad1_ : 15;
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u8 BlockWidth() const {
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return 1; // blockWidthLog2 only supports a value of 0
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}
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u8 BlockHeight() const {
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return static_cast<u8>(1 << blockHeightLog2);
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}
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u8 BlockDepth() const {
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return static_cast<u8>(1 << blockDepthLog2);
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}
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};
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/**
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* @brief The target image's metadata for any rendering operations
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* @note Any render target with ColorFormat::None as their format are effectively disabled
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*/
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struct ColorTarget {
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Address offset;
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u32 width;
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u32 height;
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enum class Format : u32 {
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// F - SFloat
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// S - SInt
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// U - UInt
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// L - sRGB
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// N - SNorm
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// Z - 0
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// O - 1
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// - UNorm
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// X - Ignored
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// 8 bit formats are in BE - opposite to VK!
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Disabled = 0x0,
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RF32_GF32_BF32_AF32 = 0xC0,
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RS32_GS32_BS32_AS32 = 0xC1,
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RU32_GU32_BU32_AU32 = 0xC2,
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RF32_GF32_BF32_X32 = 0xC3,
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RS32_GS32_BS32_X32 = 0xC4,
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RU32_GU32_BU32_X32 = 0xC5,
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R16_G16_B16_A16 = 0xC6,
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RN16_GN16_BN16_AN16 = 0xC7,
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RS16_GS16_BS16_AS16 = 0xC8,
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RU16_GU16_BU16_AU16 = 0xC9,
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RF16_GF16_BF16_AF16 = 0xCA,
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RF32_GF32 = 0xCB,
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RS32_GS32 = 0xCC,
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RU32_GU32 = 0xCD,
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RF16_GF16_BF16_X16 = 0xCE,
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A8R8G8B8 = 0xCF,
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A8RL8GL8BL8 = 0xD0,
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A2B10G10R10 = 0xD1,
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AU2BU10GU10RU10 = 0xD2,
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A8B8G8R8 = 0xD5,
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A8BL8GL8RL8 = 0xD6,
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AN8BN8GN8RN8 = 0xD7,
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AS8BS8GS8RS8 = 0xD8,
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AU8BU8GU8RU8 = 0xD9,
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R16_G16 = 0xDA,
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RN16_GN16 = 0xDB,
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RS16_GS16 = 0xDC,
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RU16_GU16 = 0xDD,
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RF16_GF16 = 0xDE,
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A2R10G10B10 = 0xDF,
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BF10GF11RF11 = 0xE0,
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RS32 = 0xE3,
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RU32 = 0xE4,
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RF32 = 0xE5,
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X8R8G8B8 = 0xE6,
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X8RL8GL8BL8 = 0xE7,
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R5G6B5 = 0xE8,
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A1R5G5B5 = 0xE9,
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G8R8 = 0xEA,
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GN8RN8 = 0xEB,
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GS8RS8 = 0xEC,
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GU8RU8 = 0xED,
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R16 = 0xEE,
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RN16 = 0xEF,
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RS16 = 0xF0,
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RU16 = 0xF1,
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RF16 = 0xF2,
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R8 = 0xF3,
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RN8 = 0xF4,
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RS8 = 0xF5,
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RU8 = 0xF6,
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A8 = 0xF7,
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X1R5G5B5 = 0xF8,
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X8B8G8R8 = 0xF9,
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X8BL8GL8RL8 = 0xFA,
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Z1R5G5B5 = 0xFB,
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O1R5G5B5 = 0xFC,
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Z8R8G8B8 = 0xFD,
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O8R8G8B8 = 0xFE,
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R32 = 0xFF,
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A16 = 0x40,
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AF16 = 0x41,
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AF32 = 0x42,
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A8R8 = 0x43,
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R16_A16 = 0x44,
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RF16_AF16 = 0x45,
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RF32_AF32 = 0x46,
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B8G8R8A8 = 0x47,
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} format;
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TargetMemory memory;
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u32 thirdDimension : 28;
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u8 _pad0_ : 4;
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u32 arrayPitchLsr2; //!< The length of the stride of a layer shifted right by 2 bits
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u32 layerOffset;
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u32 _pad1_[0x7];
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u32 ArrayPitch() const {
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return arrayPitchLsr2 << 2;
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}
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};
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static_assert(sizeof(ColorTarget) == (0x10 * sizeof(u32)));
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enum class ZtFormat : u32 {
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Z16 = 0x13,
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Z24S8 = 0x14,
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X8Z24 = 0x15,
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S8Z24 = 0x16,
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S8 = 0x17,
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V8Z24 = 0x18,
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ZF32 = 0x0A,
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ZF32_X24S8 = 0x19,
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X8Z24_X16V8S8 = 0x1D,
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ZF32_X16V8X8 = 0x1E,
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ZF32_X16V8S8 = 0x1F,
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};
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struct ZtBlockSize {
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u8 blockWidthLog2 : 4; //!< The width of a block in GOBs with log2 encoding, this is always assumed to be 1 as it is the only configuration the X1 supports
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u8 blockHeightLog2 : 4; //!< The height of a block in GOBs with log2 encoding
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u8 blockDepthLog2 : 4; //!< The depth of a block in GOBs with log2 encoding, this is always assumed to be 1 as it is the only configuration the X1 supports
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u32 _pad_ : 20;
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u8 BlockWidth() const {
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return 1; // blockWidthLog2 only supports a value of 0
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}
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u8 BlockHeight() const {
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return static_cast<u8>(1 << blockHeightLog2);
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}
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u8 BlockDepth() const {
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return 1;
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}
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};
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struct ZtSize {
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enum class Control : u8 {
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ThirdDimensionDefinesArraySize = 0,
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ArraySizeIsOne = 1,
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};
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u32 width : 28;
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u8 _pad0_ : 4;
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u32 height : 17;
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u16 _pad1_ : 15;
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u16 thirdDimension;
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Control control : 1;
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u16 _pad2_ : 15;
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};
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constexpr static size_t ViewportCount{16}; //!< Amount of viewports on Maxwell 3D, array size for any per-viewport parameter such as transform, scissors, etc
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/**
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* @brief The transformations applied on any primitive sent to a viewport
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*/
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struct Viewport {
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float scaleX; //!< Scales all X-axis primitive coordinates by this factor
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float scaleY;
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float scaleZ;
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float offsetX; //!< Translates all X-axis primitive coordinates by this value
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float offsetY;
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float offsetZ;
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/**
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* @brief A component swizzle applied to primitive coordinates prior to clipping/perspective divide with optional negation
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* @note This functionality is exposed via GL_NV_viewport_swizzle (OpenGL) and VK_NV_viewport_swizzle (Vulkan)
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*/
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enum class CoordinateSwizzle : u8 {
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PosX = 0,
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NegX = 1,
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PosY = 2,
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NegY = 3,
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PosZ = 4,
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NegZ = 5,
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PosW = 6,
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NegW = 7,
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};
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ENUM_STRING(CoordinateSwizzle, {
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ENUM_CASE_PAIR(PosX, "+X");
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ENUM_CASE_PAIR(NegX, "-X");
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ENUM_CASE_PAIR(PosY, "+Y");
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ENUM_CASE_PAIR(NegY, "-Y");
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ENUM_CASE_PAIR(PosZ, "+Z");
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ENUM_CASE_PAIR(NegZ, "-Z");
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ENUM_CASE_PAIR(PosW, "+W");
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ENUM_CASE_PAIR(NegW, "-W");
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})
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struct {
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CoordinateSwizzle x : 3;
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u8 _pad0_ : 1;
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CoordinateSwizzle y : 3;
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u8 _pad1_ : 1;
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CoordinateSwizzle z : 3;
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u8 _pad2_ : 1;
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CoordinateSwizzle w : 3;
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u32 _pad3_ : 17;
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} swizzle;
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/**
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* @brief The amount of subpixel bits on screen-space axes that bias if a pixel is inside a primitive for conservative rasterization
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* @note This functionality is exposed via GL_NV_conservative_raster (OpenGL) using SubpixelPrecisionBiasNV
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*/
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struct {
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u8 x : 5;
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u8 _pad0_ : 3;
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u8 y : 5;
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u32 _pad1_ : 19;
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} snapGridPrecision;
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};
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static_assert(sizeof(Viewport) == (0x8 * sizeof(u32)));
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/**
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* @brief The offset and extent of the viewport for transformation of coordinates from NDC-space (Normalized Device Coordinates) to screen-space
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* @note This is effectively unused since all this data can be derived from the viewport transform, this misses crucial data that the transform has such as depth range order and viewport axis inverse transformations
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*/
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struct ViewportClip {
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struct {
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u16 x0;
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u16 width;
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} horizontal;
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struct {
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u16 y0;
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u16 height;
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} vertical;
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float minZ;
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float maxZ;
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};
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static_assert(sizeof(ViewportClip) == (0x4 * sizeof(u32)));
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struct ClearRect {
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struct {
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u16 xMin;
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u16 xMax;
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} horizontal;
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struct {
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u16 yMin;
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u16 yMax;
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} vertical;
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};
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/**
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* @brief The method used to rasterize polygons, not to be confused with the primitive type
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* @note This functionality is exposed via glPolygonMode (OpenGL)
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*/
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enum class PolygonMode : u32 {
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Point = 0x1B00, //!< Draw a point for every vertex
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Line = 0x1B01, //!< Draw a line between all vertices
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Fill = 0x1B02, //!< Fill the area bounded by the vertices
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};
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struct PolyOffset {
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u32 pointEnable;
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u32 lineEnable;
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u32 fillEnable;
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};
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static_assert(sizeof(PolyOffset) == (0x3 * sizeof(u32)));
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/**
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* @brief A scissor which is used to reject all writes to non-masked regions
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* @note All coordinates are in screen-space as defined by the viewport
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*/
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struct Scissor {
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u32 enable; //!< Rejects non-masked writes when enabled and allows all writes otherwise
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struct {
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u16 xMin;
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u16 xMax;
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} horizontal;
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struct {
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u16 yMin;
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u16 yMax;
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} vertical;
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u32 _pad_;
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};
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static_assert(sizeof(Scissor) == (0x4 * sizeof(u32)));
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constexpr static size_t VertexStreamCount{16}; //!< The maximum amount of vertex buffers that can be bound at once
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constexpr static size_t VertexAttributeCount{32}; //!< The amount of vertex attributes that can be set
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union VertexAttribute {
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u32 raw;
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enum class Source : u8 {
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Active = 0,
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Inactive = 1,
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};
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enum class ComponentBitWidths : u8 {
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R32_G32_B32_A32 = 0x1,
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R32_G32_B32 = 0x2,
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R16_G16_B16_A16 = 0x3,
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R32_G32 = 0x4,
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R16_G16_B16 = 0x5,
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A8B8G8R8 = 0x2F,
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R8_G8_B8_A8 = 0xA,
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X8B8G8R8 = 0x33,
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A2B10G10R10 = 0x30,
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B10G11R11 = 0x31,
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R16_G16 = 0xF,
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R32 = 0x12,
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R8_G8_B8 = 0x13,
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G8R8 = 0x32,
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R8_G8 = 0x18,
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R16 = 0x1B,
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R8 = 0x1D,
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A8 = 0x34
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};
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enum class NumericalType : u8 {
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UnusedEnumDoNotUseBecaseItWillGoAway = 0,
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Snorm = 1,
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Unorm = 2,
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Sint = 3,
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Uint = 4,
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Uscaled = 5,
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Sscaled = 6,
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Float = 7,
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};
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struct {
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u8 stream : 5;
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u8 _pad0_ : 1;
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Source source : 1;
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u16 offset : 14;
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ComponentBitWidths componentBitWidths : 6;
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NumericalType numericalType : 3;
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u8 _pad1_ : 1;
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bool swapRAndB : 1;
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};
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};
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static_assert(sizeof(VertexAttribute) == sizeof(u32));
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constexpr u16 operator|(VertexAttribute::ComponentBitWidths componentBitWidths, VertexAttribute::NumericalType numericalType) {
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return static_cast<u16>(static_cast<u16>(componentBitWidths) | (static_cast<u16>(numericalType) << 6));
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}
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/**
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* @brief A descriptor that controls how the RenderTarget array (at 0x200) will be interpreted
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*/
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struct CtSelect {
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u8 count : 4; //!< The amount of active render targets, doesn't necessarily mean bound
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u8 target0 : 3; //!< The index of the render target that maps to slot 0
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u8 target1 : 3;
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u8 target2 : 3;
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u8 target3 : 3;
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u8 target4 : 3;
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u8 target5 : 3;
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u8 target6 : 3;
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u8 target7 : 3;
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size_t operator[](size_t index) const {
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switch (index) {
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case 0:
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return target0;
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case 1:
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return target1;
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case 2:
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return target2;
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case 3:
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return target3;
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case 4:
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return target4;
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case 5:
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return target5;
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case 6:
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return target6;
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case 7:
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return target7;
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default:
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throw exception("Invalid RT index is being mapped: {}", index);
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}
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}
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};
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static_assert(sizeof(CtSelect) == sizeof(u32));
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constexpr static size_t BlendColorChannelCount{4}; //!< The amount of color channels in operations such as blending
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enum class BlendOp : u32 {
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OglFuncSubtract = 0x0000800A,
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OglFuncReverseSubtract = 0x0000800B,
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OglFuncAdd = 0x00008006,
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OglMin = 0x00008007,
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OglMax = 0x00008008,
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D3DAdd = 0x00000001,
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D3DSubtract = 0x00000002,
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D3DRevSubtract = 0x00000003,
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D3DMin = 0x00000004,
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D3DMax = 0x00000005,
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};
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enum class BlendCoeff : u32 {
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OglZero = 0x4000,
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OglOne = 0x4001,
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OglSrcColor = 0x4300,
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OglOneMinusSrcColor = 0x4301,
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OglSrcAlpha = 0x4302,
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OglOneMinusSrcAlpha = 0x4303,
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OglDstAlpha = 0x4304,
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OglOneMinusDstAlpha = 0x4305,
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OglDstColor = 0x4306,
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OglOneMinusDstColor = 0x4307,
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OglSrcAlphaSaturate = 0x4308,
|
|
OglConstantColor = 0xC001,
|
|
OglOneMinusConstantColor = 0xC002,
|
|
OglConstantAlpha = 0xC003,
|
|
OglOneMinusConstantAlpha = 0xC004,
|
|
OglSrc1Color = 0xC900,
|
|
OglInvSrc1Color = 0xC901,
|
|
OglSrc1Alpha = 0xC902,
|
|
OglInvSrc1Alpha = 0xC903,
|
|
D3DZero = 0x1,
|
|
D3DOne = 0x2,
|
|
D3DSrcColor = 0x3,
|
|
D3DInvSrcColor = 0x4,
|
|
D3DSrcAlpha = 0x5,
|
|
D3DInvSrcAlpha = 0x6,
|
|
D3DDstAlpha = 0x7,
|
|
D3DInvDstAlpha = 0x8,
|
|
D3DDstColor = 0x9,
|
|
D3DInvDstColor = 0xA,
|
|
D3DSrcAlphaSaturate = 0xB,
|
|
D3DBlendCoeff = 0xE,
|
|
D3DInvBlendCoeff = 0xF,
|
|
D3DSrc1Color = 0x10,
|
|
D3DInvSrc1Color = 0x11,
|
|
D3DSrc1Alpha = 0x12,
|
|
D3DInvSrc1Alpha = 0x13,
|
|
};
|
|
|
|
struct ZtSelect {
|
|
u8 targetCount : 1;
|
|
u32 _pad_ : 31;
|
|
};
|
|
|
|
struct MultisampleControl {
|
|
bool alphaToCoverage : 1;
|
|
u8 _pad0_ : 3;
|
|
bool alphaToOne : 1;
|
|
u32 _pad1_ : 27;
|
|
};
|
|
static_assert(sizeof(MultisampleControl) == sizeof(u32));
|
|
|
|
struct SamplerBinding {
|
|
enum class Value : u8 {
|
|
Independently = 0,
|
|
ViaHeaderBinding = 1
|
|
};
|
|
|
|
Value value : 1;
|
|
u32 _pad_ : 31;
|
|
};
|
|
static_assert(sizeof(SamplerBinding) == sizeof(u32));
|
|
|
|
enum class CompareFunc : u32 {
|
|
D3DNever = 1,
|
|
D3DLess = 2,
|
|
D3DEqual = 3,
|
|
D3DLessEqual = 4,
|
|
D3DGreater = 5,
|
|
D3DNotEqual = 6,
|
|
D3DGreaterEqual = 7,
|
|
D3DAlways = 8,
|
|
|
|
OglNever = 0x200,
|
|
OglLess = 0x201,
|
|
OglEqual = 0x202,
|
|
OglLEqual = 0x203,
|
|
OglGreater = 0x204,
|
|
OglNotEqual = 0x205,
|
|
OglGEqual = 0x206,
|
|
OglAlways = 0x207,
|
|
};
|
|
|
|
struct StencilOps {
|
|
enum class Op : u32 {
|
|
OglZero = 0,
|
|
D3DKeep = 1,
|
|
D3DZero = 2,
|
|
D3DReplace = 3,
|
|
D3DIncrSat = 4,
|
|
D3DDecrSat = 5,
|
|
D3DInvert = 6,
|
|
D3DIncr = 7,
|
|
D3DDecr = 8,
|
|
OglKeep = 0x1E00,
|
|
OglReplace = 0x1E01,
|
|
OglIncrSat = 0x1E02,
|
|
OglDecrSat = 0x1E03,
|
|
OglInvert = 0x150A,
|
|
OglIncr = 0x8507,
|
|
OglDecr = 0x8508
|
|
};
|
|
|
|
|
|
Op fail; // 0x4E1
|
|
Op zFail; // 0x4E2
|
|
Op zPass; // 0x4E3
|
|
CompareFunc func; // 0x4E4
|
|
};
|
|
|
|
struct StencilValues {
|
|
u32 funcRef;
|
|
u32 funcMask;
|
|
u32 mask;
|
|
};
|
|
|
|
struct BackStencilValues {
|
|
u32 funcRef;
|
|
u32 mask;
|
|
u32 funcMask;
|
|
};
|
|
|
|
struct PointCoordReplace {
|
|
u8 _unk_ : 2;
|
|
enum class CoordOrigin : u8 {
|
|
LowerLeft = 0,
|
|
UpperLeft = 1,
|
|
};
|
|
CoordOrigin origin : 1;
|
|
u16 enable : 10;
|
|
u32 _pad_ : 19;
|
|
};
|
|
static_assert(sizeof(PointCoordReplace) == sizeof(u32));
|
|
|
|
enum class DrawTopology : u16 {
|
|
Points = 0x0,
|
|
Lines = 0x1,
|
|
LineLoop = 0x2,
|
|
LineStrip = 0x3,
|
|
Triangles = 0x4,
|
|
TriangleStrip = 0x5,
|
|
TriangleFan = 0x6,
|
|
Quads = 0x7,
|
|
QuadStrip = 0x8,
|
|
Polygon = 0x9,
|
|
LineListAdjcy = 0xA,
|
|
LineStripAdjcy = 0xB,
|
|
TriangleListAdjcy = 0xC,
|
|
TriangleStripAdjcy = 0xD,
|
|
Patch = 0xE,
|
|
};
|
|
|
|
ENUM_STRING(DrawTopology, {
|
|
ENUM_CASE(Points);
|
|
ENUM_CASE(Lines);
|
|
ENUM_CASE(LineLoop);
|
|
ENUM_CASE(LineStrip);
|
|
ENUM_CASE(Triangles);
|
|
ENUM_CASE(TriangleStrip);
|
|
ENUM_CASE(TriangleFan);
|
|
ENUM_CASE(Quads);
|
|
ENUM_CASE(QuadStrip);
|
|
ENUM_CASE(Polygon);
|
|
ENUM_CASE(LineListAdjcy);
|
|
ENUM_CASE(LineStripAdjcy);
|
|
ENUM_CASE(TriangleListAdjcy);
|
|
ENUM_CASE(TriangleStripAdjcy);
|
|
ENUM_CASE(Patch);
|
|
})
|
|
|
|
enum class FrontFace : u32 {
|
|
CW = 0x900,
|
|
CCW = 0x901,
|
|
};
|
|
|
|
enum class CullFace : u32 {
|
|
Front = 0x404,
|
|
Back = 0x405,
|
|
FrontAndBack = 0x408,
|
|
};
|
|
|
|
union ViewportClipControl {
|
|
u32 raw;
|
|
enum class PixelZ : u8 {
|
|
Clip = 0,
|
|
Clamp = 1
|
|
};
|
|
|
|
enum class GuardbandScale : u8 {
|
|
Scale256,
|
|
Scale1
|
|
};
|
|
|
|
enum class GeometryClip : u8 {
|
|
WZeroClip = 0,
|
|
Passthru = 1,
|
|
FrustrumXYClip = 2,
|
|
FrustrumXYZClip = 3,
|
|
WZeroClipNoZCull = 4,
|
|
FrustrumZClip = 5,
|
|
WZeroTriFillOrClip = 6
|
|
};
|
|
|
|
enum class GuardbandZScale : u8 {
|
|
SameAsXYGuardband = 0,
|
|
Scale256 = 1,
|
|
Scale1 = 2
|
|
};
|
|
|
|
struct {
|
|
bool minZZeroMaxZOne : 1;
|
|
GuardbandZScale guardbandZScale : 2;
|
|
PixelZ pixelMinZ : 1;
|
|
PixelZ pixelMaxZ : 1;
|
|
u8 _pad1_ : 2;
|
|
GuardbandScale geometryGuardbandScale : 1;
|
|
u8 _pad2_ : 2;
|
|
GuardbandScale linePointCullGuardbandScale : 1;
|
|
GeometryClip geometryClip : 3;
|
|
u32 _pad3_ : 18;
|
|
};
|
|
};
|
|
static_assert(sizeof(ViewportClipControl) == sizeof(u32));
|
|
|
|
union CtWrite {
|
|
bool Any() const {
|
|
return rEnable || gEnable || bEnable || aEnable;
|
|
}
|
|
|
|
u32 raw;
|
|
|
|
struct {
|
|
bool rEnable : 1;
|
|
u8 _pad0_ : 3;
|
|
bool gEnable : 1;
|
|
u8 _pad1_ : 3;
|
|
bool bEnable : 1;
|
|
u8 _pad2_ : 3;
|
|
bool aEnable : 1;
|
|
u32 _pad3_ : 19;
|
|
};
|
|
};
|
|
static_assert(sizeof(CtWrite) == sizeof(u32));
|
|
|
|
/**
|
|
* @brief A method call which causes a layer of an RT to be cleared with a channel mask
|
|
*/
|
|
struct ClearSurface {
|
|
bool zEnable : 1; //!< If the depth channel should be cleared
|
|
bool stencilEnable : 1;
|
|
bool rEnable : 1;
|
|
bool gEnable : 1;
|
|
bool bEnable : 1;
|
|
bool aEnable : 1;
|
|
u8 mrtSelect : 4; //!< The ID of the render target to clear
|
|
u16 rtArrayIndex : 11; //!< The index of the layer of the render target to clear
|
|
u16 _pad_ : 10;
|
|
};
|
|
static_assert(sizeof(ClearSurface) == sizeof(u32));
|
|
|
|
struct SemaphoreInfo {
|
|
enum class Op : u8 {
|
|
Release = 0,
|
|
Acquire = 1,
|
|
Counter = 2,
|
|
Trap = 3,
|
|
};
|
|
|
|
enum class ReductionOp : u8 {
|
|
Add = 0,
|
|
Min = 1,
|
|
Max = 2,
|
|
Inc = 3,
|
|
Dec = 4,
|
|
And = 5,
|
|
Or = 6,
|
|
Xor = 7,
|
|
};
|
|
|
|
enum class Unit : u8 {
|
|
VFetch = 1,
|
|
VP = 2,
|
|
Rast = 4,
|
|
StrmOut = 5,
|
|
GP = 6,
|
|
ZCull = 7,
|
|
Prop = 10,
|
|
Crop = 15,
|
|
};
|
|
|
|
enum class SyncCondition : u8 {
|
|
NotEqual = 0,
|
|
GreaterThan = 1,
|
|
};
|
|
|
|
enum class Format : u8 {
|
|
U32 = 0,
|
|
I32 = 1,
|
|
};
|
|
|
|
enum class CounterType : u8 {
|
|
Zero = 0x0,
|
|
InputVertices = 0x1,
|
|
InputPrimitives = 0x3,
|
|
VertexShaderInvocations = 0x5,
|
|
GeometryShaderInvocations = 0x7,
|
|
GeometryShaderPrimitives = 0x9,
|
|
ZcullStats0 = 0xA,
|
|
TransformFeedbackPrimitivesWritten = 0xB,
|
|
ZcullStats1 = 0xC,
|
|
ZcullStats2 = 0xE,
|
|
ClipperInputPrimitives = 0xF,
|
|
ZcullStats3 = 0x10,
|
|
ClipperOutputPrimitives = 0x11,
|
|
PrimitivesGenerated = 0x12,
|
|
FragmentShaderInvocations = 0x13,
|
|
SamplesPassed = 0x15,
|
|
TransformFeedbackOffset = 0x1A,
|
|
TessControlShaderInvocations = 0x1B,
|
|
TessEvaluationShaderInvocations = 0x1D,
|
|
TessEvaluationShaderPrimitives = 0x1F,
|
|
};
|
|
|
|
enum class StructureSize : u8 {
|
|
FourWords = 0,
|
|
OneWord = 1,
|
|
};
|
|
|
|
Op op : 2;
|
|
bool flushDisable : 1;
|
|
bool reductionEnable : 1;
|
|
bool fenceEnable : 1;
|
|
u8 _pad0_ : 4;
|
|
ReductionOp reductionOp : 3;
|
|
Unit unit : 4;
|
|
SyncCondition syncCondition : 1;
|
|
Format format : 2;
|
|
u8 _pad1_ : 1;
|
|
bool awakenEnable : 1;
|
|
u8 _pad2_ : 2;
|
|
CounterType counterType : 5;
|
|
StructureSize structureSize : 1;
|
|
};
|
|
static_assert(sizeof(SemaphoreInfo) == sizeof(u32));
|
|
|
|
constexpr static size_t ShaderStageCount{5}; //!< Amount of pipeline stages on Maxwell 3D
|
|
|
|
/**
|
|
* @brief All the pipeline stages that Maxwell3D supports for draws
|
|
*/
|
|
enum class ShaderStage {
|
|
Vertex = 0,
|
|
TessellationControl = 1,
|
|
TessellationEvaluation = 2,
|
|
Geometry = 3,
|
|
Fragment = 4,
|
|
};
|
|
|
|
struct ConstantBufferSelector {
|
|
u32 size : 17;
|
|
u16 _pad_ : 15;
|
|
Address address;
|
|
};
|
|
static_assert(sizeof(ConstantBufferSelector) == sizeof(u32) * 3);
|
|
|
|
struct BindGroup {
|
|
u32 _pad0_[4];
|
|
union {
|
|
struct {
|
|
u32 valid : 1;
|
|
u32 _pad1_ : 3;
|
|
u32 shaderSlot : 5; //!< The index of the constant buffer in the pipeline stage to bind to
|
|
};
|
|
u32 raw;
|
|
} constantBuffer;
|
|
u32 _pad2_[3];
|
|
};
|
|
static_assert(sizeof(BindGroup) == (sizeof(u32) * 8));
|
|
|
|
constexpr static size_t ShaderStageConstantBufferCount{18}; //!< Maximum amount of constant buffers that can be bound to a single pipeline stage
|
|
|
|
constexpr static size_t PipelineCount{6}; //!< Amount of shader stages on Maxwell 3D
|
|
|
|
/**
|
|
* @brief The arguments to set a shader program for a pipeline stage
|
|
*/
|
|
struct Pipeline {
|
|
struct Shader {
|
|
enum class Type : u8 {
|
|
VertexCullBeforeFetch = 0,
|
|
Vertex = 1,
|
|
TessellationInit = 2,
|
|
Tessellation = 3,
|
|
Geometry = 4,
|
|
Pixel = 5,
|
|
};
|
|
|
|
bool enable : 1;
|
|
u8 _pad0_ : 3;
|
|
Type type : 4;
|
|
u32 _pad1_ : 24;
|
|
} shader;
|
|
u32 programOffset; //!< Offset from the base shader memory IOVA
|
|
u32 _pad2_;
|
|
u8 registerCount; //!< Amount of GPRs used by the shader program
|
|
u32 _pad3_ : 24;
|
|
u8 bindingGroup : 3;
|
|
u32 _pad4_ : 29;
|
|
u32 _pad5_[11];
|
|
};
|
|
static_assert(sizeof(Pipeline) == (sizeof(u32) * 0x10));
|
|
|
|
struct ProvokingVertex {
|
|
enum class Value : u8 {
|
|
First = 0,
|
|
Last = 1,
|
|
} value : 1;
|
|
u32 _pad_ : 31;
|
|
};
|
|
static_assert(sizeof(ProvokingVertex) == sizeof(u32));
|
|
|
|
struct ZtLayer {
|
|
u16 offset;
|
|
u16 _pad_;
|
|
};
|
|
|
|
struct IndexBuffer {
|
|
Address address, limit; //!< The IOVA bounds of the index buffer
|
|
enum class IndexSize : u32 {
|
|
OneByte = 0,
|
|
TwoBytes = 1,
|
|
FourBytes = 2,
|
|
} indexSize;
|
|
u32 first;
|
|
};
|
|
|
|
enum class ZClipRange : u32 {
|
|
NegativeWToPositiveW = 0,
|
|
ZeroToPositiveW = 1
|
|
};
|
|
|
|
constexpr static size_t StreamOutBufferCount{4}; //!< Number of supported transform feecback buffers in the 3D engine
|
|
|
|
struct StreamOutBuffer {
|
|
u32 enable;
|
|
Address address;
|
|
u32 size;
|
|
u32 loadWritePointerStartOffset;
|
|
u32 _pad_[3];
|
|
};
|
|
static_assert(sizeof(StreamOutBuffer) == (sizeof(u32) * 8));
|
|
|
|
struct StreamOutControl {
|
|
u8 streamSelect : 2;
|
|
u32 _pad0_ : 30;
|
|
u8 componentCount : 8;
|
|
u32 _pad1_ : 24;
|
|
u32 strideBytes;
|
|
u32 _pad_;
|
|
};
|
|
static_assert(sizeof(StreamOutControl) == (sizeof(u32) * 4));
|
|
|
|
constexpr static size_t StreamOutLayoutSelectAttributeCount{0x80};
|
|
|
|
struct VertexStream {
|
|
union {
|
|
u32 raw;
|
|
struct {
|
|
u32 stride : 12;
|
|
u32 enable : 1;
|
|
};
|
|
} format;
|
|
Address location;
|
|
u32 frequency;
|
|
};
|
|
static_assert(sizeof(VertexStream) == sizeof(u32) * 4);
|
|
|
|
struct BlendPerTarget {
|
|
bool seperateForAlpha : 1;
|
|
u32 _pad0_ : 31;
|
|
BlendOp colorOp;
|
|
BlendCoeff colorSourceCoeff;
|
|
BlendCoeff colorDestCoeff;
|
|
BlendOp alphaOp;
|
|
BlendCoeff alphaSourceCoeff;
|
|
BlendCoeff alphaDestCoeff;
|
|
u32 _pad_;
|
|
};
|
|
|
|
struct Blend {
|
|
bool seperateForAlpha : 1;
|
|
u32 _pad0_ : 31;
|
|
BlendOp colorOp;
|
|
BlendCoeff colorSourceCoeff;
|
|
BlendCoeff colorDestCoeff;
|
|
BlendOp alphaOp;
|
|
BlendCoeff alphaSourceCoeff;
|
|
bool globalColorKeyEnable : 1;
|
|
u32 _pad1_ : 31;
|
|
BlendCoeff alphaDestCoeff;
|
|
bool singleRopControlEnable : 1;
|
|
u32 _pad2_ : 31;
|
|
std::array<u32, ColorTargetCount> enable;
|
|
};
|
|
|
|
struct WindowOrigin {
|
|
bool lowerLeft : 1;
|
|
u8 _pad0_ : 3;
|
|
bool flipY : 1;
|
|
u32 _pad1_ : 27;
|
|
};
|
|
static_assert(sizeof(WindowOrigin) == sizeof(u32));
|
|
|
|
struct SurfaceClip {
|
|
struct {
|
|
u16 x;
|
|
u16 width;
|
|
} horizontal;
|
|
|
|
struct {
|
|
u16 y;
|
|
u16 height;
|
|
} vertical;
|
|
};
|
|
static_assert(sizeof(SurfaceClip) == sizeof(u32) * 2);
|
|
|
|
struct ClearSurfaceControl {
|
|
bool respectStencilMask : 1;
|
|
u8 _pad0_ : 3;
|
|
bool useClearRect : 1;
|
|
u8 _pad1_ : 3;
|
|
bool useScissor0 : 1;
|
|
u8 _pad2_ : 3;
|
|
bool useViewportClip0 : 1;
|
|
u32 _pad3_ : 19;
|
|
};
|
|
static_assert(sizeof(ClearSurfaceControl) == sizeof(u32));
|
|
|
|
struct VertexStreamInstance {
|
|
bool isInstanced : 1;
|
|
u32 _pad0_ : 31;
|
|
};
|
|
static_assert(sizeof(VertexStreamInstance) == sizeof(u32));
|
|
|
|
struct PrimitiveTopologyControl {
|
|
enum class Override : u8 {
|
|
UseTopologyInBeginMethods = 0,
|
|
UseSeperateTopologyState = 1
|
|
};
|
|
|
|
Override override : 1;
|
|
u32 _pad0_ : 31;
|
|
};
|
|
static_assert(sizeof(PrimitiveTopologyControl) == sizeof(u32));
|
|
|
|
enum class PrimitiveTopology : u16 {
|
|
PointList = 0x1,
|
|
LineList = 0x2,
|
|
LineStrip = 0x3,
|
|
TriangleList = 0x4,
|
|
TriangleStrip = 0x5,
|
|
LineListAdjcy = 0xA,
|
|
LineStripAdjcy = 0xB,
|
|
TriangleListAdjcy = 0xC,
|
|
TriangleStripAdjcy = 0xD,
|
|
PatchList = 0xE,
|
|
LegacyPoints = 0x1001,
|
|
LegacyIndexedLineList = 0x1002,
|
|
LegacyIndexedTriangleList = 0x1003,
|
|
LegacyLineList = 0x100F,
|
|
LegacyLineStrip = 0x1010,
|
|
LegacyIndexedLineStrip = 0x1011,
|
|
LegacyTriangleList = 0x1012,
|
|
LegacyTriangleStrip = 0x1013,
|
|
LegacyIndexedTriangleStrip = 0x1014,
|
|
LegacyTriangleFan = 0x1015,
|
|
LegacyIndexedTriangleFan = 0x1016,
|
|
LegacyTriangleFanImm = 0x1017,
|
|
LegacyLineListImm = 0x1018,
|
|
LegacyIndexedTriangleList2 = 0x101A,
|
|
LegacyIndexedLineList2 = 0x101B
|
|
};
|
|
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inline DrawTopology ConvertPrimitiveTopologyToDrawTopology(PrimitiveTopology topology) {
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switch (topology) {
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case PrimitiveTopology::PointList:
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case PrimitiveTopology::LegacyPoints:
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return DrawTopology::Points;
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case PrimitiveTopology::LineList:
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case PrimitiveTopology::LegacyLineList:
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return DrawTopology::Lines;
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case PrimitiveTopology::LineStrip:
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case PrimitiveTopology::LegacyLineStrip:
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return DrawTopology::LineStrip;
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case PrimitiveTopology::TriangleList:
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case PrimitiveTopology::LegacyTriangleList:
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return DrawTopology::Triangles;
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case PrimitiveTopology::TriangleStrip:
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case PrimitiveTopology::LegacyTriangleStrip:
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return DrawTopology::TriangleStrip;
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case PrimitiveTopology::LegacyTriangleFan:
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return DrawTopology::TriangleFan;
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case PrimitiveTopology::LineListAdjcy:
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return DrawTopology::LineListAdjcy;
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case PrimitiveTopology::LineStripAdjcy:
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return DrawTopology::LineStripAdjcy;
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case PrimitiveTopology::TriangleListAdjcy:
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return DrawTopology::TriangleListAdjcy;
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case PrimitiveTopology::TriangleStripAdjcy:
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return DrawTopology::TriangleStripAdjcy;
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case PrimitiveTopology::PatchList:
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return DrawTopology::Patch;
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default:
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throw exception("Unsupported primitive topology 0x{:X}", static_cast<u16>(topology));
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}
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}
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struct TessellationParameters {
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enum class DomainType : u8 {
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Isoline = 0,
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Triangle = 1,
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Quad = 2
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};
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enum class Spacing : u8 {
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Integer = 0,
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FractionalOdd = 1,
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FractionalEven = 2
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};
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enum class OutputPrimitives : u8 {
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Points = 0,
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Lines = 1,
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TrianglesCW = 2,
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TrianglesCCW = 3
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};
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DomainType domainType : 2;
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u8 _pad0_ : 2;
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Spacing spacing : 2;
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u8 _pad1_ : 2;
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OutputPrimitives outputPrimitives : 2;
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u32 _pad2_ : 22;
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};
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static_assert(sizeof(TessellationParameters) == sizeof(u32));
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struct LogicOp {
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bool enable : 1;
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u32 _pad0_ : 31;
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enum class Func : u32 {
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Clear = 0x1500,
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And = 0x1501,
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AndReverse = 0x1502,
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Copy = 0x1503,
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AndInverted = 0x1504,
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Noop = 0x1505,
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Xor = 0x1506,
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Or = 0x1507,
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Nor = 0x1508,
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Equiv = 0x1509,
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Invert = 0x150A,
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OrReverse = 0x150B,
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CopyInverted = 0x150C,
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OrInverted = 0x150D,
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Nand = 0x150E,
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Set = 0x150F
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} func;
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};
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#pragma pack(pop)
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}
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