mirror of
https://github.com/skyline-emu/skyline.git
synced 2024-06-02 10:18:46 +02:00
a1d90f053a
This commit implements tracing Skyline using https://perfetto.dev/ for SVCs, IPC, Scheduler and Presentation
314 lines
15 KiB
C++
314 lines
15 KiB
C++
// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <cxxabi.h>
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#include <unistd.h>
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#include "common/signal.h"
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#include "common/tracing.h"
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#include "os.h"
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#include "jvm.h"
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#include "kernel/types/KProcess.h"
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#include "kernel/svc.h"
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#include "nce/guest.h"
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#include "nce/instructions.h"
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#include "nce.h"
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namespace skyline::nce {
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void NCE::SvcHandler(u16 svc, ThreadContext *ctx) {
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TRACE_EVENT_END("guest");
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const auto &state{*ctx->state};
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try {
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auto function{kernel::svc::SvcTable[svc]};
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if (function) [[likely]] {
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TRACE_EVENT("kernel", "SVC");
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state.logger->Debug("SVC called 0x{:X}", svc);
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(*function)(state);
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} else [[unlikely]] {
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throw exception("Unimplemented SVC 0x{:X}", svc);
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}
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while (kernel::Scheduler::YieldPending) [[unlikely]] {
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state.scheduler->Rotate(false);
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kernel::Scheduler::YieldPending = false;
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state.scheduler->WaitSchedule();
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}
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} catch (const signal::SignalException &e) {
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if (e.signal != SIGINT) {
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state.logger->Error("{} (SVC: 0x{:X})\nStack Trace:{}", e.what(), svc, state.loader->GetStackTrace(e.frames));
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if (state.thread->id) {
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signal::BlockSignal({SIGINT});
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state.process->Kill(false);
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}
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}
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abi::__cxa_end_catch(); // We call this prior to the longjmp to cause the exception object to be destroyed
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std::longjmp(state.thread->originalCtx, true);
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} catch (const std::exception &e) {
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state.logger->Error("{} (SVC: 0x{:X})\nStack Trace:{}", e.what(), svc, state.loader->GetStackTrace());
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if (state.thread->id) {
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signal::BlockSignal({SIGINT});
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state.process->Kill(false);
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}
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abi::__cxa_end_catch();
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std::longjmp(state.thread->originalCtx, true);
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}
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TRACE_EVENT_BEGIN("guest", "Guest");
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}
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void NCE::SignalHandler(int signal, siginfo *info, ucontext *ctx, void **tls) {
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if (*tls) { // If TLS was restored then this occurred in guest code
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auto &mctx{ctx->uc_mcontext};
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const auto &state{*reinterpret_cast<ThreadContext *>(*tls)->state};
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if (signal != SIGINT) {
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signal::StackFrame topFrame{.lr = reinterpret_cast<void *>(ctx->uc_mcontext.pc), .next = reinterpret_cast<signal::StackFrame *>(ctx->uc_mcontext.regs[29])};
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std::string trace{state.loader->GetStackTrace(&topFrame)};
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std::string cpuContext;
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if (mctx.fault_address)
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cpuContext += fmt::format("\n Fault Address: 0x{:X}", mctx.fault_address);
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if (mctx.sp)
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cpuContext += fmt::format("\n Stack Pointer: 0x{:X}", mctx.sp);
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for (u8 index{}; index < (sizeof(mcontext_t::regs) / sizeof(u64)); index += 2)
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cpuContext += fmt::format("\n X{:<2}: 0x{:<16X} X{:<2}: 0x{:X}", index, mctx.regs[index], index + 1, mctx.regs[index + 1]);
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state.logger->Error("Thread #{} has crashed due to signal: {}\nStack Trace:{}\nCPU Context:{}", state.thread->id, strsignal(signal), trace, cpuContext);
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if (state.thread->id) {
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signal::BlockSignal({SIGINT});
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state.process->Kill(false);
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}
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}
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mctx.pc = reinterpret_cast<u64>(&std::longjmp);
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mctx.regs[0] = reinterpret_cast<u64>(state.thread->originalCtx);
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mctx.regs[1] = true;
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*tls = nullptr;
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} else { // If TLS wasn't restored then this occurred in host code
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signal::ExceptionalSignalHandler(signal, info, ctx); //!< Delegate throwing a host exception to the exceptional signal handler
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}
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}
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void *NceTlsRestorer() {
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ThreadContext *threadCtx;
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asm volatile("MRS %x0, TPIDR_EL0":"=r"(threadCtx));
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if (threadCtx->magic != constant::SkyTlsMagic)
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return nullptr;
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asm volatile("MSR TPIDR_EL0, %x0"::"r"(threadCtx->hostTpidrEl0));
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return threadCtx;
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}
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NCE::NCE(const DeviceState &state) : state(state) {
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signal::SetTlsRestorer(&NceTlsRestorer);
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}
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constexpr u8 MainSvcTrampolineSize{17}; // Size of the main SVC trampoline function in u32 units
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constexpr u32 TpidrEl0{0x5E82}; // ID of TPIDR_EL0 in MRS
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constexpr u32 TpidrroEl0{0x5E83}; // ID of TPIDRRO_EL0 in MRS
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constexpr u32 CntfrqEl0{0x5F00}; // ID of CNTFRQ_EL0 in MRS
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constexpr u32 CntpctEl0{0x5F01}; // ID of CNTPCT_EL0 in MRS
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constexpr u32 CntvctEl0{0x5F02}; // ID of CNTVCT_EL0 in MRS
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constexpr u32 TegraX1Freq{19200000}; // The clock frequency of the Tegra X1 (19.2 MHz)
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NCE::PatchData NCE::GetPatchData(const std::vector<u8> &text) {
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size_t size{guest::SaveCtxSize + guest::LoadCtxSize + MainSvcTrampolineSize};
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std::vector<size_t> offsets;
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u64 frequency;
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asm("MRS %0, CNTFRQ_EL0" : "=r"(frequency));
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bool rescaleClock{frequency != TegraX1Freq};
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auto start{reinterpret_cast<const u32 *>(text.data())}, end{reinterpret_cast<const u32 *>(text.data() + text.size())};
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for (const u32 *instruction{start}; instruction < end; instruction++) {
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auto svc{*reinterpret_cast<const instructions::Svc *>(instruction)};
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auto mrs{*reinterpret_cast<const instructions::Mrs *>(instruction)};
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auto msr{*reinterpret_cast<const instructions::Msr *>(instruction)};
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if (svc.Verify()) {
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size += 7;
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offsets.push_back(instruction - start);
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} else if (mrs.Verify()) {
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if (mrs.srcReg == TpidrroEl0 || mrs.srcReg == TpidrEl0) {
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size += ((mrs.destReg != registers::X0) ? 6 : 3);
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offsets.push_back(instruction - start);
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} else {
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if (rescaleClock) {
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if (mrs.srcReg == CntpctEl0) {
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size += guest::RescaleClockSize + 3;
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offsets.push_back(instruction - start);
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} else if (mrs.srcReg == CntfrqEl0) {
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size += 3;
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offsets.push_back(instruction - start);
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}
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} else if (mrs.srcReg == CntpctEl0) {
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offsets.push_back(instruction - start);
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}
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}
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} else if (msr.Verify() && msr.destReg == TpidrEl0) {
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size += 6;
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offsets.push_back(instruction - start);
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}
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}
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return {util::AlignUp(size * sizeof(u32), PAGE_SIZE), offsets};
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}
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void NCE::PatchCode(std::vector<u8> &text, u32 *patch, size_t patchSize, const std::vector<size_t> &offsets) {
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u32 *start{patch};
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u32 *end{patch + (patchSize / sizeof(u32))};
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std::memcpy(patch, reinterpret_cast<void *>(&guest::SaveCtx), guest::SaveCtxSize * sizeof(u32));
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patch += guest::SaveCtxSize;
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{
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/* Main SVC Trampoline */
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/* Store LR in 16B of pre-allocated stack */
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*patch++ = 0xF90007FE; // STR LR, [SP, #8]
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/* Replace Skyline TLS with host TLS */
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*patch++ = 0xD53BD041; // MRS X1, TPIDR_EL0
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*patch++ = 0xF9415022; // LDR X2, [X1, #0x2A0] (ThreadContext::hostTpidrEl0)
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/* Replace guest stack with host stack */
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*patch++ = 0xD51BD042; // MSR TPIDR_EL0, X2
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*patch++ = 0x910003E2; // MOV X2, SP
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*patch++ = 0xF9415423; // LDR X3, [X1, #0x2A8] (ThreadContext::hostSp)
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*patch++ = 0x9100007F; // MOV SP, X3
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/* Store Skyline TLS + guest SP on stack */
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*patch++ = 0xA9BF0BE1; // STP X1, X2, [SP, #-16]!
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/* Jump to SvcHandler */
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for (const auto &mov : instructions::MoveRegister(registers::X2, reinterpret_cast<u64>(&NCE::SvcHandler)))
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if (mov)
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*patch++ = mov;
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*patch++ = 0xD63F0040; // BLR X2
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/* Restore Skyline TLS + guest SP */
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*patch++ = 0xA8C10BE1; // LDP X1, X2, [SP], #16
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*patch++ = 0xD51BD041; // MSR TPIDR_EL0, X1
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*patch++ = 0x9100005F; // MOV SP, X2
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/* Restore LR and Return */
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*patch++ = 0xF94007FE; // LDR LR, [SP, #8]
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*patch++ = 0xD65F03C0; // RET
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}
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std::memcpy(patch, reinterpret_cast<void *>(&guest::LoadCtx), guest::LoadCtxSize * sizeof(u32));
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patch += guest::LoadCtxSize;
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u64 frequency;
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asm("MRS %0, CNTFRQ_EL0" : "=r"(frequency));
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bool rescaleClock{frequency != TegraX1Freq};
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for (auto offset : offsets) {
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u32 *instruction{reinterpret_cast<u32 *>(text.data()) + offset};
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auto svc{*reinterpret_cast<instructions::Svc *>(instruction)};
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auto mrs{*reinterpret_cast<instructions::Mrs *>(instruction)};
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auto msr{*reinterpret_cast<instructions::Msr *>(instruction)};
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if (svc.Verify()) {
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/* Per-SVC Trampoline */
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/* Rewrite SVC with B to trampoline */
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*instruction = instructions::B((end - patch) + offset, true).raw;
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/* Save Context */
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*patch++ = 0xF81F0FFE; // STR LR, [SP, #-16]!
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*patch = instructions::BL(start - patch).raw;
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patch++;
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/* Jump to main SVC trampoline */
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*patch++ = instructions::Movz(registers::W0, static_cast<u16>(svc.value)).raw;
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*patch = instructions::BL((start - patch) + guest::SaveCtxSize).raw;
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patch++;
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/* Restore Context and Return */
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*patch = instructions::BL((start - patch) + guest::SaveCtxSize + MainSvcTrampolineSize).raw;
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patch++;
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*patch++ = 0xF84107FE; // LDR LR, [SP], #16
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*patch = instructions::B((end - patch) + offset + 1).raw;
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patch++;
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} else if (mrs.Verify()) {
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if (mrs.srcReg == TpidrroEl0 || mrs.srcReg == TpidrEl0) {
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/* Emulated TLS Register Load */
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/* Rewrite MRS with B to trampoline */
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*instruction = instructions::B((end - patch) + offset, true).raw;
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/* Allocate Scratch Register */
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if (mrs.destReg != registers::X0)
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*patch++ = 0xF81F0FE0; // STR X0, [SP, #-16]!
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/* Retrieve emulated TLS register from ThreadContext */
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*patch++ = 0xD53BD040; // MRS X0, TPIDR_EL0
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if (mrs.srcReg == TpidrroEl0)
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*patch++ = 0xF9415800; // LDR X0, [X0, #0x2B0] (ThreadContext::tpidrroEl0)
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else
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*patch++ = 0xF9415C00; // LDR X0, [X0, #0x2B8] (ThreadContext::tpidrEl0)
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/* Restore Scratch Register and Return */
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if (mrs.destReg != registers::X0) {
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*patch++ = instructions::Mov(registers::X(mrs.destReg), registers::X0).raw;
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*patch++ = 0xF84107E0; // LDR X0, [SP], #16
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}
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*patch = instructions::B((end - patch) + offset + 1).raw;
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patch++;
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} else {
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if (rescaleClock) {
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if (mrs.srcReg == CntpctEl0) {
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/* Physical Counter Load Emulation (With Rescaling) */
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/* Rewrite MRS with B to trampoline */
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*instruction = instructions::B((end - patch) + offset, true).raw;
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/* Rescale host clock */
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std::memcpy(patch, reinterpret_cast<void *>(&guest::RescaleClock), guest::RescaleClockSize * sizeof(u32));
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patch += guest::RescaleClockSize;
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/* Load result from stack into destination register */
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instructions::Ldr ldr(0xF94003E0); // LDR XOUT, [SP]
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ldr.destReg = mrs.destReg;
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*patch++ = ldr.raw;
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/* Free 32B stack allocation by RescaleClock and Return */
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*patch++ = {0x910083FF}; // ADD SP, SP, #32
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*patch = instructions::B((end - patch) + offset + 1).raw;
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patch++;
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} else if (mrs.srcReg == CntfrqEl0) {
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/* Physical Counter Frequency Load Emulation */
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/* Rewrite MRS with B to trampoline */
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*instruction = instructions::B((end - patch) + offset, true).raw;
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/* Write back Tegra X1 Counter Frequency and Return */
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for (const auto &mov : instructions::MoveRegister(registers::X(mrs.destReg), TegraX1Freq))
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*patch++ = mov;
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*patch = instructions::B((end - patch) + offset + 1).raw;
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patch++;
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}
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} else if (mrs.srcReg == CntpctEl0) {
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/* Physical Counter Load Emulation (Without Rescaling) */
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// We just convert CNTPCT_EL0 -> CNTVCT_EL0 as Linux doesn't allow access to the physical counter
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*instruction = instructions::Mrs(CntvctEl0, registers::X(mrs.destReg)).raw;
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}
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}
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} else if (msr.Verify() && msr.destReg == TpidrEl0) {
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/* Emulated TLS Register Store */
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/* Rewrite MSR with B to trampoline */
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*instruction = instructions::B((end - patch) + offset, true).raw;
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/* Allocate Scratch Registers */
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bool x0x1{mrs.srcReg != registers::X0 && mrs.srcReg != registers::X1};
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*patch++ = x0x1 ? 0xA9BF07E0 : 0xA9BF0FE2; // STP X(0/2), X(1/3), [SP, #-16]!
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/* Store new TLS value into ThreadContext */
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*patch++ = x0x1 ? 0xD53BD040 : 0xD53BD042; // MRS X(0/2), TPIDR_EL0
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*patch++ = instructions::Mov(x0x1 ? registers::X1 : registers::X3, registers::X(msr.srcReg)).raw;
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*patch++ = x0x1 ? 0xF9015C01 : 0xF9015C03; // STR X(1/3), [X0, #0x4B8] (ThreadContext::tpidrEl0)
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/* Restore Scratch Registers and Return */
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*patch++ = x0x1 ? 0xA8C107E0 : 0xA8C10FE2; // LDP X(0/2), X(1/3), [SP], #16
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*patch = instructions::B((end - patch) + offset + 1).raw;
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patch++;
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}
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}
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}
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}
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