352 lines
12 KiB
C++
352 lines
12 KiB
C++
// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <csignal>
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#include <cstdlib>
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#include <initializer_list> // This is used implicitly
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#include <asm/siginfo.h>
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#include "guest_common.h"
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#define FORCE_INLINE __attribute__((always_inline)) inline // NOLINT(cppcoreguidelines-macro-usage)
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namespace skyline::guest {
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FORCE_INLINE void SaveCtxStack() {
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asm("SUB SP, SP, #240\n\t"
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"STP X0, X1, [SP, #0]\n\t"
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"STP X2, X3, [SP, #16]\n\t"
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"STP X4, X5, [SP, #32]\n\t"
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"STP X6, X7, [SP, #48]\n\t"
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"STP X8, X9, [SP, #64]\n\t"
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"STP X10, X11, [SP, #80]\n\t"
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"STP X12, X13, [SP, #96]\n\t"
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"STP X14, X15, [SP, #112]\n\t"
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"STP X16, X17, [SP, #128]\n\t"
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"STP X18, X19, [SP, #144]\n\t"
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"STP X20, X21, [SP, #160]\n\t"
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"STP X22, X23, [SP, #176]\n\t"
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"STP X24, X25, [SP, #192]\n\t"
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"STP X26, X27, [SP, #208]\n\t"
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"STP X28, X29, [SP, #224]"
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);
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}
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FORCE_INLINE void LoadCtxStack() {
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asm("LDP X0, X1, [SP, #0]\n\t"
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"LDP X2, X3, [SP, #16]\n\t"
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"LDP X4, X5, [SP, #32]\n\t"
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"LDP X6, X7, [SP, #48]\n\t"
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"LDP X8, X9, [SP, #64]\n\t"
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"LDP X10, X11, [SP, #80]\n\t"
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"LDP X12, X13, [SP, #96]\n\t"
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"LDP X14, X15, [SP, #112]\n\t"
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"LDP X16, X17, [SP, #128]\n\t"
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"LDP X18, X19, [SP, #144]\n\t"
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"LDP X20, X21, [SP, #160]\n\t"
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"LDP X22, X23, [SP, #176]\n\t"
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"LDP X24, X25, [SP, #192]\n\t"
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"LDP X26, X27, [SP, #208]\n\t"
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"LDP X28, X29, [SP, #224]\n\t"
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"ADD SP, SP, #240"
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);
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}
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FORCE_INLINE void SaveCtxTls() {
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asm("STR LR, [SP, #-16]!\n\t"
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"MRS LR, TPIDR_EL0\n\t"
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"STP X0, X1, [LR, #16]\n\t"
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"STP X2, X3, [LR, #32]\n\t"
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"STP X4, X5, [LR, #48]\n\t"
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"STP X6, X7, [LR, #64]\n\t"
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"STP X8, X9, [LR, #80]\n\t"
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"STP X10, X11, [LR, #96]\n\t"
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"STP X12, X13, [LR, #112]\n\t"
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"STP X14, X15, [LR, #128]\n\t"
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"STP X16, X17, [LR, #144]\n\t"
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"STP X18, X19, [LR, #160]\n\t"
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"STP X20, X21, [LR, #176]\n\t"
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"STP X22, X23, [LR, #192]\n\t"
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"STP X24, X25, [LR, #208]\n\t"
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"STP X26, X27, [LR, #224]\n\t"
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"STP X28, X29, [LR, #240]\n\t"
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"LDR LR, [SP], #16\n\t"
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"DSB ST"
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);
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}
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FORCE_INLINE void LoadCtxTls() {
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asm("STR LR, [SP, #-16]!\n\t"
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"MRS LR, TPIDR_EL0\n\t"
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"LDP X0, X1, [LR, #16]\n\t"
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"LDP X2, X3, [LR, #32]\n\t"
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"LDP X4, X5, [LR, #48]\n\t"
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"LDP X6, X7, [LR, #64]\n\t"
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"LDP X8, X9, [LR, #80]\n\t"
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"LDP X10, X11, [LR, #96]\n\t"
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"LDP X12, X13, [LR, #112]\n\t"
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"LDP X14, X15, [LR, #128]\n\t"
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"LDP X16, X17, [LR, #144]\n\t"
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"LDP X18, X19, [LR, #160]\n\t"
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"LDP X20, X21, [LR, #176]\n\t"
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"LDP X22, X23, [LR, #192]\n\t"
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"LDP X24, X25, [LR, #208]\n\t"
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"LDP X26, X27, [LR, #224]\n\t"
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"LDP X28, X29, [LR, #240]\n\t"
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"LDR LR, [SP], #16"
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);
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}
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/**
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* @note Do not use any functions that cannot be inlined from this, as this function is placed at an arbitrary address in the guest. In addition, do not use any static variables or globals as the .bss section is not copied into the guest.
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*/
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void SvcHandler(u64 pc, u32 svc) {
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volatile ThreadContext *ctx;
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asm("MRS %0, TPIDR_EL0":"=r"(ctx));
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ctx->pc = pc;
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ctx->commandId = svc;
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if (svc == 0xB) { // svcSleepThread
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switch (ctx->registers.x0) {
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case 0:
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case 1:
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case 2: {
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asm("MOV X0, XZR\n\t"
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"MOV X1, XZR\n\t"
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"MOV X2, XZR\n\t"
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"MOV X3, XZR\n\t"
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"MOV X4, XZR\n\t"
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"MOV X5, XZR\n\t"
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"MOV X8, #124\n\t" // __NR_sched_yield
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"STR LR, [SP, #-16]!\n\t"
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"MOV LR, SP\n\t"
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"SVC #0\n\t"
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"MOV SP, LR\n\t"
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"LDR LR, [SP], #16":: : "x0", "x1", "x2", "x3", "x4", "x5", "x8");
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break;
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}
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default: {
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struct timespec spec = {
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.tv_sec = static_cast<time_t>(ctx->registers.x0 / 1000000000),
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.tv_nsec = static_cast<long>(ctx->registers.x0 % 1000000000)
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};
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asm("MOV X0, %0\n\t"
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"MOV X1, XZR\n\t"
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"MOV X2, XZR\n\t"
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"MOV X3, XZR\n\t"
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"MOV X4, XZR\n\t"
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"MOV X5, XZR\n\t"
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"MOV X8, #101\n\t" // __NR_nanosleep
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"STR LR, [SP, #-16]!\n\t"
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"MOV LR, SP\n\t"
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"SVC #0\n\t"
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"MOV SP, LR\n\t"
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"LDR LR, [SP], #16"::"r"(&spec) : "x0", "x1", "x2", "x3", "x4", "x5", "x8");
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}
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}
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return;
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} else if (svc == 0x1E) { // svcGetSystemTick
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asm("STP X1, X2, [SP, #-16]!\n\t"
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"STR Q0, [SP, #-16]!\n\t"
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"STR Q1, [SP, #-16]!\n\t"
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"STR Q2, [SP, #-16]!\n\t"
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"MRS X1, CNTFRQ_EL0\n\t"
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"MRS X2, CNTVCT_EL0\n\t"
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"UCVTF D0, X0\n\t"
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"MOV X1, 87411174408192\n\t"
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"MOVK X1, 0x4172, LSL 48\n\t"
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"FMOV D2, X1\n\t"
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"UCVTF D1, X1\n\t"
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"FDIV D0, D0, D2\n\t"
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"FMUL D0, D0, D1\n\t"
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"FCVTZU %0, D0\n\t"
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"LDR Q2, [SP], #16\n\t"
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"LDR Q1, [SP], #16\n\t"
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"LDR Q0, [SP], #16\n\t"
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"LDP X1, X2, [SP], #16"::"r"(ctx->registers.x0));
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return;
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}
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while (true) {
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ctx->state = ThreadState::WaitKernel;
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while (ctx->state == ThreadState::WaitKernel);
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if (ctx->state == ThreadState::WaitRun) {
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break;
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} else if (ctx->state == ThreadState::WaitFunc) {
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if (ctx->commandId == static_cast<u32>(ThreadCall::Syscall)) {
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SaveCtxStack();
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LoadCtxTls();
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asm("STR LR, [SP, #-16]!\n\t"
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"MOV LR, SP\n\t"
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"SVC #0\n\t"
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"MOV SP, LR\n\t"
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"LDR LR, [SP], #16");
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SaveCtxTls();
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LoadCtxStack();
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} else if (ctx->commandId == static_cast<u32>(ThreadCall::Memcopy)) {
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auto src = reinterpret_cast<u8 *>(ctx->registers.x0);
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auto dest = reinterpret_cast<u8 *>(ctx->registers.x1);
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auto size = ctx->registers.x2;
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auto end = src + size;
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while (src < end)
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*(src++) = *(dest++);
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} else if (ctx->commandId == static_cast<u32>(ThreadCall::Clone)) {
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SaveCtxStack();
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LoadCtxTls();
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asm("STR LR, [SP, #-16]!\n\t"
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"MOV LR, SP\n\t"
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"SVC #0\n\t"
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"CBNZ X0, .parent\n\t"
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"MSR TPIDR_EL0, X3\n\t"
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"MOV LR, 0\n\t"
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"MOV X0, X6\n\t"
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"MOV X1, XZR\n\t"
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"MOV X2, XZR\n\t"
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"MOV X3, XZR\n\t"
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"MOV X4, XZR\n\t"
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"MOV X6, XZR\n\t"
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"MOV X7, XZR\n\t"
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"MOV X8, XZR\n\t"
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"MOV X9, XZR\n\t"
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"MOV X10, XZR\n\t"
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"MOV X11, XZR\n\t"
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"MOV X12, XZR\n\t"
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"MOV X13, XZR\n\t"
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"MOV X14, XZR\n\t"
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"MOV X15, XZR\n\t"
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"MOV X16, XZR\n\t"
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"MOV X17, XZR\n\t"
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"MOV X18, XZR\n\t"
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"MOV X19, XZR\n\t"
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"MOV X20, XZR\n\t"
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"MOV X21, XZR\n\t"
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"MOV X22, XZR\n\t"
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"MOV X23, XZR\n\t"
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"MOV X24, XZR\n\t"
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"MOV X25, XZR\n\t"
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"MOV X26, XZR\n\t"
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"MOV X27, XZR\n\t"
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"MOV X28, XZR\n\t"
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"MOV X29, XZR\n\t"
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"BR X5\n\t"
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".parent:\n\t"
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"MOV SP, LR\n\t"
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"LDR LR, [SP], #16");
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SaveCtxTls();
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LoadCtxStack();
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}
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}
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}
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ctx->state = ThreadState::Running;
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}
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void SignalHandler(int signal, siginfo_t *info, ucontext_t *ucontext) {
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volatile ThreadContext *ctx;
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asm("MRS %0, TPIDR_EL0":"=r"(ctx));
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for (u8 index = 0; index < 30; index++)
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ctx->registers.regs[index] = ucontext->uc_mcontext.regs[index];
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ctx->pc = ucontext->uc_mcontext.pc;
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ctx->commandId = static_cast<u32>(signal);
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ctx->faultAddress = ucontext->uc_mcontext.fault_address;
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ctx->sp = ucontext->uc_mcontext.sp;
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while (true) {
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ctx->state = ThreadState::GuestCrash;
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if (ctx->state == ThreadState::WaitRun)
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exit(0);
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}
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}
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void GuestEntry(u64 address) {
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volatile ThreadContext *ctx;
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asm("MRS %0, TPIDR_EL0":"=r"(ctx));
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while (true) {
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ctx->state = ThreadState::WaitInit;
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while (ctx->state == ThreadState::WaitInit);
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if (ctx->state == ThreadState::WaitRun) {
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break;
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} else if (ctx->state == ThreadState::WaitFunc) {
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if (ctx->commandId == static_cast<u32>(ThreadCall::Syscall)) {
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SaveCtxStack();
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LoadCtxTls();
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asm("STR LR, [SP, #-16]!\n\t"
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"MOV LR, SP\n\t"
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"SVC #0\n\t"
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"MOV SP, LR\n\t"
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"LDR LR, [SP], #16");
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SaveCtxTls();
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LoadCtxStack();
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}
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} else if (ctx->commandId == static_cast<u32>(ThreadCall::Memcopy)) {
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auto src = reinterpret_cast<u8 *>(ctx->registers.x0);
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auto dest = reinterpret_cast<u8 *>(ctx->registers.x1);
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auto size = ctx->registers.x2;
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auto end = src + size;
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while (src < end)
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*(src++) = *(dest++);
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}
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}
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struct sigaction sigact{
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.sa_sigaction = reinterpret_cast<void (*)(int, struct siginfo *, void *)>(reinterpret_cast<void *>(SignalHandler)),
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.sa_flags = SA_SIGINFO,
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};
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for (int signal : {SIGILL, SIGTRAP, SIGBUS, SIGFPE, SIGSEGV})
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sigaction(signal, &sigact, nullptr);
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ctx->state = ThreadState::Running;
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asm("MOV LR, %0\n\t"
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"MOV X0, %1\n\t"
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"MOV X1, %2\n\t"
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"MOV X2, XZR\n\t"
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"MOV X3, XZR\n\t"
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"MOV X4, XZR\n\t"
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"MOV X5, XZR\n\t"
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"MOV X6, XZR\n\t"
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"MOV X7, XZR\n\t"
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"MOV X8, XZR\n\t"
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"MOV X9, XZR\n\t"
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"MOV X10, XZR\n\t"
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"MOV X11, XZR\n\t"
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"MOV X12, XZR\n\t"
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"MOV X13, XZR\n\t"
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"MOV X14, XZR\n\t"
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"MOV X15, XZR\n\t"
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"MOV X16, XZR\n\t"
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"MOV X17, XZR\n\t"
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"MOV X18, XZR\n\t"
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"MOV X19, XZR\n\t"
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"MOV X20, XZR\n\t"
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"MOV X21, XZR\n\t"
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"MOV X22, XZR\n\t"
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"MOV X23, XZR\n\t"
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"MOV X24, XZR\n\t"
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"MOV X25, XZR\n\t"
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"MOV X26, XZR\n\t"
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"MOV X27, XZR\n\t"
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"MOV X28, XZR\n\t"
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"MOV X29, XZR\n\t"
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"RET"::"r"(address), "r"(ctx->registers.x0), "r"(ctx->registers.x1) : "x0", "x1", "lr");
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__builtin_unreachable();
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}
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}
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