452 lines
17 KiB
C++
452 lines
17 KiB
C++
// SPDX-License-Identifier: MPL-2.0
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// Copyright © 2020 Skyline Team and Contributors (https://github.com/skyline-emu/)
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#include <common.h>
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namespace skyline {
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namespace regs {
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enum X { X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30 };
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enum W { W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, W16, W17, W18, W19, W20, W21, W22, W23, W24, W25, W26, W27, W28, W29, W30 };
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enum S { Sp, Pc };
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}
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namespace instr {
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/**
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* @brief A bit-field struct that encapsulates a BRK instruction. See https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/brk-breakpoint-instruction.
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*/
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struct Brk {
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/**
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* @brief Creates a BRK instruction with a specific immediate value, used for generating BRK opcodes
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* @param value The immediate value of the instruction
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*/
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inline constexpr Brk(u16 value) {
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sig0 = 0x0;
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this->value = value;
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sig1 = 0x6A1;
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid BRK instruction
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*/
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inline constexpr bool Verify() {
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return (sig0 == 0x0 && sig1 == 0x6A1);
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}
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union {
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struct {
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u8 sig0 : 5; //!< 5-bit signature (0x0)
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u32 value : 16; //!< 16-bit immediate value
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u16 sig1 : 11; //!< 11-bit signature (0x6A1)
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Brk) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a SVC instruction. See https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/svc-supervisor-call.
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*/
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struct Svc {
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid SVC instruction
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*/
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inline constexpr bool Verify() {
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return (sig0 == 0x1 && sig1 == 0x6A0);
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}
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union {
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struct {
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u8 sig0 : 5; //!< 5-bit signature (0x0)
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u32 value : 16; //!< 16-bit immediate value
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u16 sig1 : 11; //!< 11-bit signature (0x6A1)
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Svc) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a MRS instruction. See https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/mrs-move-system-register.
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*/
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struct Mrs {
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/**
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* @brief Creates a MRS instruction, used for generating BRK opcodes
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* @param srcReg The source system register
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* @param dstReg The destination Xn register
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*/
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inline constexpr Mrs(u32 srcReg, regs::X dstReg) {
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this->srcReg = srcReg;
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this->destReg = dstReg;
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sig = 0xD53;
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid MRS instruction
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*/
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inline constexpr bool Verify() {
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return (sig == 0xD53);
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}
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union {
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struct {
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u8 destReg : 5; //!< 5-bit destination register
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u32 srcReg : 15; //!< 15-bit source register
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u16 sig : 12; //!< 16-bit signature (0xD53)
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Mrs) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a B instruction. See https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/b-branch.
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*/
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struct B {
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public:
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/**
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* @brief Creates a B instruction with a specific offset
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* @param offset The offset to encode in the instruction (Should be 32-bit aligned)
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*/
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inline constexpr B(i64 offset) {
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this->offset = static_cast<i32>(offset / 4);
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sig = 0x5;
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}
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/**
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* @brief Returns the offset of the instruction
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* @return The offset encoded within the instruction
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*/
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inline constexpr i32 Offset() {
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return offset * 4;
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid Branch instruction
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*/
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inline constexpr bool Verify() {
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return (sig == 0x5);
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}
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union {
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struct {
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i32 offset : 26; //!< 26-bit branch offset
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u8 sig : 6; //!< 6-bit signature (0x5)
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(B) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a BL instruction. See https://developer.arm.com/docs/ddi0596/latest/base-instructions-alphabetic-order/b-branch.
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*/
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struct BL {
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public:
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/**
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* @brief Creates a BL instruction with a specific offset
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* @param offset The offset to encode in the instruction (Should be 32-bit aligned)
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*/
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inline constexpr BL(i64 offset) {
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this->offset = static_cast<i32>(offset / 4);
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sig = 0x25;
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}
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/**
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* @brief Returns the offset of the instruction
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* @return The offset encoded within the instruction
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*/
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inline constexpr i32 Offset() {
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return offset * 4;
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid Branch Linked instruction
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*/
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inline constexpr bool Verify() {
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return (sig == 0x25);
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}
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union {
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struct {
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i32 offset : 26; //!< 26-bit branch offset
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u8 sig : 6; //!< 6-bit signature (0x25)
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(BL) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a MOVZ instruction. See https://developer.arm.com/docs/ddi0596/e/base-instructions-alphabetic-order/movz-move-wide-with-zero.
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*/
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struct Movz {
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public:
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/**
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* @brief Creates a MOVZ instruction
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* @param destReg The destination Xn register to store the value in
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* @param imm16 The 16-bit value to store
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* @param shift The offset (in bits and 16-bit aligned) in the register to store the value at
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*/
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inline constexpr Movz(regs::X destReg, u16 imm16, u8 shift = 0) {
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this->destReg = static_cast<u8>(destReg);
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this->imm16 = imm16;
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hw = static_cast<u8>(shift / 16);
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sig = 0xA5;
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sf = 1;
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}
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/**
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* @brief Creates a MOVZ instruction
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* @param destReg The destination Wn register to store the value in
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* @param imm16 The 16-bit value to store
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* @param shift The offset (in bits and 16-bit aligned) in the register to store the value at
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*/
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inline constexpr Movz(regs::W destReg, u16 imm16, u8 shift = 0) {
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this->destReg = static_cast<u8>(destReg);
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this->imm16 = imm16;
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hw = static_cast<u8>(shift / 16);
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sig = 0xA5;
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sf = 0;
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}
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/**
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* @brief Returns the offset of the instruction
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* @return The offset encoded within the instruction
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*/
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inline constexpr u8 Shift() {
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return static_cast<u8>(hw * 16);
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid MOVZ instruction
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*/
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inline constexpr bool Verify() {
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return (sig == 0xA5);
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}
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union {
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struct __attribute__((packed)) {
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u8 destReg : 5; //!< 5-bit destination register
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u16 imm16 : 16; //!< 16-bit immediate value
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u8 hw : 2; //!< 2-bit offset
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u8 sig : 8; //!< 8-bit signature (0xA5)
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u8 sf : 1; //!< 1-bit register type
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Movz) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a MOVK instruction. See https://developer.arm.com/docs/ddi0596/e/base-instructions-alphabetic-order/movk-move-wide-with-keep.
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*/
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struct Movk {
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public:
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/**
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* @brief Creates a MOVK instruction
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* @param destReg The destination Xn register to store the value in
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* @param imm16 The 16-bit value to store
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* @param shift The offset (in bits and 16-bit aligned) in the register to store the value at
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*/
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inline constexpr Movk(regs::X destReg, u16 imm16, u8 shift = 0) {
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this->destReg = static_cast<u8>(destReg);
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this->imm16 = imm16;
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hw = static_cast<u8>(shift / 16);
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sig = 0xE5;
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sf = 1;
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}
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/**
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* @brief Creates a MOVK instruction
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* @param destReg The destination Wn register to store the value in
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* @param imm16 The 16-bit value to store
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* @param shift The offset (in bits and 16-bit aligned) in the register to store the value at
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*/
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inline constexpr Movk(regs::W destReg, u16 imm16, u8 shift = 0) {
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this->destReg = static_cast<u8>(destReg);
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this->imm16 = imm16;
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hw = static_cast<u8>(shift / 16);
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sig = 0xE5;
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sf = 0;
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}
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/**
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* @brief Returns the offset of the instruction
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* @return The offset encoded within the instruction
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*/
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inline constexpr u8 Shift() {
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return static_cast<u8>(hw * 16);
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid MOVK instruction
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*/
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inline constexpr bool Verify() {
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return (sig == 0xE5);
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}
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union {
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struct __attribute__((packed)) {
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u8 destReg : 5; //!< 5-bit destination register
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u16 imm16 : 16; //!< 16-bit immediate value
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u8 hw : 2; //!< 2-bit offset
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u8 sig : 8; //!< 8-bit signature (0xA5)
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u8 sf : 1; //!< 1-bit register type
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Movk) == sizeof(u32));
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/**
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* @param destReg The destination register of the operation
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* @param value The 64-bit value to insert into the register
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* @return A vector with the instructions to insert the value
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*/
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inline const std::vector<u32> MoveU64Reg(regs::X destReg, u64 value) {
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union {
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u64 val;
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struct {
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u16 v0;
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u16 v16;
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u16 v32;
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u16 v48;
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};
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} val;
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val.val = value;
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std::vector<u32> instr;
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instr::Movz mov0(destReg, val.v0, 0);
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instr.push_back(mov0.raw);
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instr::Movk mov16(destReg, val.v16, 16);
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if (val.v16)
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instr.push_back(mov16.raw);
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instr::Movk mov32(destReg, val.v32, 32);
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if (val.v32)
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instr.push_back(mov32.raw);
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instr::Movk mov48(destReg, val.v48, 48);
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if (val.v48)
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instr.push_back(mov48.raw);
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return instr;
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}
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/**
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* @param destReg The destination register of the operation
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* @param value The 32-bit value to insert into the register
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* @return A vector with the instructions to insert the value
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*/
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inline const std::vector<u32> MoveU32Reg(regs::X destReg, u32 value) {
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union {
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u32 val;
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struct {
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u16 v0;
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u16 v16;
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};
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} val;
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val.val = value;
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std::vector<u32> instr;
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instr::Movz mov0(destReg, val.v0, 0);
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instr.push_back(mov0.raw);
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instr::Movk mov16(destReg, val.v16, 16);
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if (val.v16)
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instr.push_back(mov16.raw);
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return instr;
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}
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/**
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* @brief A bit-field struct that encapsulates a MOV (Register) instruction. See https://developer.arm.com/docs/ddi0596/e/base-instructions-alphabetic-order/mov-register-move-register-an-alias-of-orr-shifted-register.
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*/
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struct Mov {
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public:
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/**
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* @brief Creates a MOV (Register) instruction
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* @param destReg The destination Xn register to store the value in
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* @param srcReg The source Xn register to retrieve the value from
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*/
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inline constexpr Mov(regs::X destReg, regs::X srcReg) {
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this->destReg = static_cast<u8>(destReg);
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sig0 = 0x1F;
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imm6 = 0;
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this->srcReg = static_cast<u8>(srcReg);
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sig1 = 0x150;
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sf = 1;
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}
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/**
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* @brief Creates a MOV instruction
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* @param destReg The destination Wn register to store the value in
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* @param srcReg The source Wn register to retrieve the value from
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*/
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inline constexpr Mov(regs::W destReg, regs::W srcReg) {
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this->destReg = static_cast<u8>(destReg);
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sig0 = 0x1F;
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imm6 = 0;
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this->srcReg = static_cast<u8>(srcReg);
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sig1 = 0x150;
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sf = 0;
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}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid MOVZ instruction
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*/
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inline constexpr bool Verify() {
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return (sig0 == 0x1F) && (sig1 == 0x150);
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}
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union {
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struct __attribute__((packed)) {
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u8 destReg : 5; //!< 5-bit destination register
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u8 sig0 : 5; //!< 5-bit signature (0x1F)
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u8 imm6 : 6; //!< 6-bit immediate value
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u8 srcReg : 5; //!< 5-bit source register
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u16 sig1 : 10; //!< 10-bit signature (0x150)
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u8 sf : 1; //!< 1-bit register type
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Mov) == sizeof(u32));
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/**
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* @brief A bit-field struct that encapsulates a LDR (immediate) instruction. See https://developer.arm.com/docs/ddi0596/e/base-instructions-alphabetic-order/ldr-immediate-load-register-immediate.
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*/
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struct Ldr {
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public:
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/**
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* @brief Creates a LDR (immediate) instruction
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* @param raw The raw value of the whole instruction
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*/
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inline constexpr Ldr(u32 raw) : raw(raw) {}
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/**
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* @brief Returns if the opcode is valid or not
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* @return If the opcode represents a valid FCVTZU instruction
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*/
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inline constexpr bool Verify() {
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return (sig0 == 0x0 && sig1 == 0x1CA && sig2 == 0x1);
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}
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union {
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struct __attribute__((packed)) {
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u8 destReg : 5; //!< 5-bit destination register
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u8 srcReg : 5; //!< 5-bit source register
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u8 sig0 : 2; //!< 2-bit signature (0x0)
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u16 imm : 9; //!< 6-bit immediate value
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u16 sig1 : 9; //!< 9-bit signature (0x1CA)
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u8 sf : 1; //!< 1-bit register type
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u8 sig2 : 1; //!< 1-bit signature (0x1)
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};
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u32 raw{}; //!< The raw value of the instruction
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};
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};
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static_assert(sizeof(Ldr) == sizeof(u32));
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}
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}
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