2008-08-06 03:09:59 +02:00
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/**********************************************************************************
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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2008-10-16 03:49:58 +02:00
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(c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and
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2008-08-06 03:09:59 +02:00
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Jerremy Koot (jkoot@snes9x.com)
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(c) Copyright 2002 - 2004 Matthew Kendora
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(c) Copyright 2002 - 2005 Peter Bortas (peter@bortas.org)
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(c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/)
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(c) Copyright 2001 - 2006 John Weidman (jweidman@slip.net)
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2008-10-16 03:49:58 +02:00
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(c) Copyright 2002 - 2006 Brad Jorsch (anomie@users.sourceforge.net),
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funkyass (funkyass@spam.shaw.ca),
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Kris Bleakley (codeviolation@hotmail.com),
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Nach (n-a-c-h@users.sourceforge.net), and
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2008-08-06 03:09:59 +02:00
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zones (kasumitokoduck@yahoo.com)
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BS-X C emulator code
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(c) Copyright 2005 - 2006 Dreamer Nom,
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zones
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C4 x86 assembler and some C emulation code
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(c) Copyright 2000 - 2003 _Demo_ (_demo_@zsnes.com),
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Nach,
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zsKnight (zsknight@zsnes.com)
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C4 C++ code
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(c) Copyright 2003 - 2006 Brad Jorsch,
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Nach
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DSP-1 emulator code
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(c) Copyright 1998 - 2006 _Demo_,
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Andreas Naive (andreasnaive@gmail.com)
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Gary Henderson,
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Ivar (ivar@snes9x.com),
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John Weidman,
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Kris Bleakley,
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Matthew Kendora,
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Nach,
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neviksti (neviksti@hotmail.com)
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DSP-2 emulator code
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(c) Copyright 2003 John Weidman,
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Kris Bleakley,
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Lord Nightmare (lord_nightmare@users.sourceforge.net),
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Matthew Kendora,
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neviksti
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DSP-3 emulator code
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(c) Copyright 2003 - 2006 John Weidman,
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Kris Bleakley,
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Lancer,
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z80 gaiden
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DSP-4 emulator code
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(c) Copyright 2004 - 2006 Dreamer Nom,
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John Weidman,
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Kris Bleakley,
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Nach,
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z80 gaiden
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OBC1 emulator code
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(c) Copyright 2001 - 2004 zsKnight,
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pagefault (pagefault@zsnes.com),
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Kris Bleakley,
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Ported from x86 assembler to C by sanmaiwashi
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SPC7110 and RTC C++ emulator code
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(c) Copyright 2002 Matthew Kendora with research by
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zsKnight,
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John Weidman,
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Dark Force
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S-DD1 C emulator code
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(c) Copyright 2003 Brad Jorsch with research by
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Andreas Naive,
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John Weidman
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S-RTC C emulator code
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(c) Copyright 2001-2006 byuu,
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John Weidman
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ST010 C++ emulator code
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(c) Copyright 2003 Feather,
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John Weidman,
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Kris Bleakley,
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Matthew Kendora
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Super FX x86 assembler emulator code
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(c) Copyright 1998 - 2003 _Demo_,
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pagefault,
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zsKnight,
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Super FX C emulator code
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(c) Copyright 1997 - 1999 Ivar,
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Gary Henderson,
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John Weidman
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Sound DSP emulator code is derived from SNEeSe and OpenSPC:
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(c) Copyright 1998 - 2003 Brad Martin
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(c) Copyright 1998 - 2006 Charles Bilyue'
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SH assembler code partly based on x86 assembler code
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(c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se)
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2xSaI filter
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(c) Copyright 1999 - 2001 Derek Liauw Kie Fa
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2008-10-16 03:49:58 +02:00
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HQ2x filter
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2008-08-06 03:09:59 +02:00
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(c) Copyright 2003 Maxim Stepin (maxim@hiend3d.com)
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Specific ports contains the works of other authors. See headers in
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individual files.
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Snes9x homepage: http://www.snes9x.com
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Permission to use, copy, modify and/or distribute Snes9x in both binary
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2008-10-16 03:49:58 +02:00
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and source form, for non-commercial purposes, is hereby granted without
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fee, providing that this license information and copyright notice appear
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2008-08-06 03:09:59 +02:00
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with all copies and any derived work.
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This software is provided 'as-is', without any express or implied
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warranty. In no event shall the authors be held liable for any damages
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arising from the use of this software or it's derivatives.
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Snes9x is freeware for PERSONAL USE only. Commercial users should
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seek permission of the copyright holders first. Commercial use includes,
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but is not limited to, charging money for Snes9x or software derived from
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Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
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using Snes9x as a promotion for your commercial product.
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The copyright holders request that bug fixes and improvements to the code
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should be forwarded to them so everyone can benefit from the modifications
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in future versions.
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Super NES and Super Nintendo Entertainment System are trademarks of
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Nintendo Co., Limited and its subsidiary companies.
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**********************************************************************************/
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#ifndef _PPU_H_
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#define _PPU_H_
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#define FIRST_VISIBLE_LINE 1
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extern uint8 GetBank;
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extern uint16 SignExtend [2];
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#define TILE_2BIT 0
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#define TILE_4BIT 1
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#define TILE_8BIT 2
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#define TILE_2BIT_EVEN 3
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#define TILE_2BIT_ODD 4
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#define TILE_4BIT_EVEN 5
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#define TILE_4BIT_ODD 6
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#define MAX_2BIT_TILES 4096
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#define MAX_4BIT_TILES 2048
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#define MAX_8BIT_TILES 1024
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#define PPU_H_BEAM_IRQ_SOURCE (1 << 0)
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#define PPU_V_BEAM_IRQ_SOURCE (1 << 1)
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#define GSU_IRQ_SOURCE (1 << 2)
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#define SA1_IRQ_SOURCE (1 << 7)
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#define SA1_DMA_IRQ_SOURCE (1 << 5)
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struct ClipData {
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uint8 Count;
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uint8 DrawMode[6];
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uint16 Left[6];
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uint16 Right[6];
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};
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struct InternalPPU {
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bool8 ColorsChanged;
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uint8 HDMA;
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uint8 HDMAEnded;
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uint8 MaxBrightness;
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bool8 LatchedBlanking;
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bool8 OBJChanged;
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bool8 RenderThisFrame;
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bool8 DirectColourMapsNeedRebuild;
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uint32 FrameCount;
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uint32 RenderedFramesCount;
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uint32 DisplayedRenderedFrameCount;
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uint32 SkippedFrames;
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uint32 FrameSkip;
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uint8 *TileCache [7];
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uint8 *TileCached [7];
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#ifdef CORRECT_VRAM_READS
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uint16 VRAMReadBuffer;
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#else
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bool8 FirstVRAMRead;
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#endif
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bool8 Interlace;
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bool8 InterlaceOBJ;
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bool8 PseudoHires;
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bool8 DoubleWidthPixels;
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bool8 DoubleHeightPixels;
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int RenderedScreenHeight;
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int RenderedScreenWidth;
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uint32 Red [256];
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uint32 Green [256];
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uint32 Blue [256];
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uint8 *XB;
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uint16 ScreenColors [256];
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int PreviousLine;
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int CurrentLine;
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struct ClipData Clip[2][6];
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};
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struct SOBJ
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{
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short HPos;
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uint16 VPos;
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uint16 Name;
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uint8 VFlip;
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uint8 HFlip;
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uint8 Priority;
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uint8 Palette;
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uint8 Size;
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};
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struct SPPU {
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uint8 BGMode;
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uint8 BG3Priority;
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uint8 Brightness;
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struct {
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bool8 High;
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uint8 Increment;
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uint16 Address;
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uint16 Mask1;
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uint16 FullGraphicCount;
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uint16 Shift;
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} VMA;
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struct {
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uint16 SCBase;
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uint16 VOffset;
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uint16 HOffset;
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uint8 BGSize;
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uint16 NameBase;
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uint16 SCSize;
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} BG [4];
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bool8 CGFLIP;
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uint16 CGDATA [256];
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uint8 FirstSprite;
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uint8 LastSprite;
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struct SOBJ OBJ [128];
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uint8 OAMPriorityRotation;
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uint16 OAMAddr;
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uint8 RangeTimeOver;
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uint8 OAMFlip;
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uint16 OAMTileAddress;
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uint16 IRQVBeamPos;
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uint16 IRQHBeamPos;
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uint16 VBeamPosLatched;
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uint16 HBeamPosLatched;
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uint8 HBeamFlip;
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uint8 VBeamFlip;
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uint8 HVBeamCounterLatched;
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short MatrixA;
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short MatrixB;
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short MatrixC;
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short MatrixD;
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short CentreX;
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short CentreY;
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short M7HOFS;
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short M7VOFS;
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uint8 CGADD;
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uint8 FixedColourRed;
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uint8 FixedColourGreen;
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uint8 FixedColourBlue;
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uint16 SavedOAMAddr;
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uint16 ScreenHeight;
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uint32 WRAM;
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uint8 BG_Forced;
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bool8 ForcedBlanking;
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bool8 OBJThroughMain;
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bool8 OBJThroughSub;
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uint8 OBJSizeSelect;
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uint16 OBJNameBase;
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bool8 OBJAddition;
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uint8 OAMReadFlip;
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uint8 OAMData [512 + 32];
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bool8 VTimerEnabled;
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bool8 HTimerEnabled;
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short HTimerPosition;
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uint8 Mosaic;
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uint8 MosaicStart;
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bool8 BGMosaic [4];
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bool8 Mode7HFlip;
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bool8 Mode7VFlip;
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uint8 Mode7Repeat;
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uint8 Window1Left;
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uint8 Window1Right;
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uint8 Window2Left;
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uint8 Window2Right;
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uint8 ClipCounts [6];
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uint8 ClipWindowOverlapLogic [6];
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uint8 ClipWindow1Enable [6];
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uint8 ClipWindow2Enable [6];
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bool8 ClipWindow1Inside [6];
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bool8 ClipWindow2Inside [6];
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bool8 RecomputeClipWindows;
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uint8 CGFLIPRead;
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uint16 OBJNameSelect;
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bool8 Need16x8Mulitply;
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uint16 OAMWriteRegister;
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uint8 BGnxOFSbyte;
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uint8 M7byte;
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uint8 OpenBus1;
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uint8 OpenBus2;
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uint16 GunVLatch;
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uint16 GunHLatch;
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short VTimerPosition;
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};
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#define CLIP_OR 0
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#define CLIP_AND 1
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#define CLIP_XOR 2
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#define CLIP_XNOR 3
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struct SDMA {
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/* $43x0 */
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bool8 TransferDirection;
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bool8 HDMAIndirectAddressing;
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bool8 UnusedBit43x0;
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bool8 AAddressFixed;
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bool8 AAddressDecrement;
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uint8 TransferMode;
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/* $43x1 */
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uint8 BAddress;
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/* $43x2-4 */
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uint16 AAddress;
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uint8 ABank;
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/* $43x5-6 */
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uint16 DMACount_Or_HDMAIndirectAddress;
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/* $43x7 */
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uint8 IndirectBank;
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/* $43x8-9 */
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uint16 Address;
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/* $43xA */
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uint8 Repeat;
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uint8 LineCount;
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/* $43xB/F */
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uint8 UnknownByte;
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/* internal */
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uint8 DoTransfer;
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};
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#define TransferBytes DMACount_Or_HDMAIndirectAddress
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#define IndirectAddress DMACount_Or_HDMAIndirectAddress
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START_EXTERN_C
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void S9xUpdateScreen ();
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void S9xResetPPU ();
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void S9xSoftResetPPU ();
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void S9xFixColourBrightness ();
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void S9xDoAutoJoypad ();
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void S9xSuperFXExec ();
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void S9xSetPPU (uint8 Byte, uint16 Address);
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uint8 S9xGetPPU (uint16 Address);
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void S9xSetCPU (uint8 Byte, uint16 Address);
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uint8 S9xGetCPU (uint16 Address);
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void S9xInitC4 ();
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void S9xSetC4 (uint8 Byte, uint16 Address);
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uint8 S9xGetC4 (uint16 Address);
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void S9xSetC4RAM (uint8 Byte, uint16 Address);
|
|
|
|
uint8 S9xGetC4RAM (uint16 Address);
|
|
|
|
uint8 *S9xGetBasePointerC4 (uint16 Address);
|
|
|
|
|
|
|
|
void S9xUpdateHVTimerPosition (void);
|
|
|
|
void S9xCheckMissingHTimerPosition (int32);
|
2008-10-16 03:49:58 +02:00
|
|
|
void S9xCheckMissingHTimerPositionRange (int32, int32);
|
|
|
|
void S9xCheckMissingVTimerPosition (void);
|
2008-08-06 03:09:59 +02:00
|
|
|
|
|
|
|
extern struct SPPU PPU;
|
|
|
|
extern struct SDMA DMA [8];
|
|
|
|
extern struct InternalPPU IPPU;
|
|
|
|
END_EXTERN_C
|
|
|
|
|
|
|
|
#include "gfx.h"
|
|
|
|
#include "memmap.h"
|
|
|
|
|
|
|
|
typedef struct{
|
|
|
|
uint8 _5C77;
|
|
|
|
uint8 _5C78;
|
|
|
|
uint8 _5A22;
|
|
|
|
} SnesModel;
|
|
|
|
|
2008-10-16 03:49:58 +02:00
|
|
|
#ifndef _GLOBALS_CPP
|
2008-08-06 03:09:59 +02:00
|
|
|
extern SnesModel* Model;
|
|
|
|
extern SnesModel M1SNES;
|
|
|
|
extern SnesModel M2SNES;
|
2008-10-16 03:49:58 +02:00
|
|
|
#endif
|
2008-08-06 03:09:59 +02:00
|
|
|
|
|
|
|
#define MAX_5C77_VERSION 0x01
|
|
|
|
#define MAX_5C78_VERSION 0x03
|
|
|
|
#define MAX_5A22_VERSION 0x02
|
|
|
|
|
|
|
|
STATIC inline uint8 REGISTER_4212()
|
|
|
|
{
|
|
|
|
GetBank = 0;
|
|
|
|
if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE &&
|
|
|
|
CPU.V_Counter < PPU.ScreenHeight + FIRST_VISIBLE_LINE + 3)
|
|
|
|
GetBank = 1;
|
|
|
|
|
2008-10-16 03:49:58 +02:00
|
|
|
GetBank |= CPU.Cycles >= Timings.HBlankStart ? 0x40 : 0;
|
2008-08-06 03:09:59 +02:00
|
|
|
if (CPU.V_Counter >= PPU.ScreenHeight + FIRST_VISIBLE_LINE)
|
|
|
|
GetBank |= 0x80; /* XXX: 0x80 or 0xc0 ? */
|
|
|
|
|
|
|
|
return (GetBank);
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void FLUSH_REDRAW ()
|
|
|
|
{
|
|
|
|
if (IPPU.PreviousLine != IPPU.CurrentLine)
|
|
|
|
S9xUpdateScreen ();
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2104 (uint8 byte)
|
|
|
|
{
|
|
|
|
if (PPU.OAMAddr & 0x100)
|
|
|
|
{
|
|
|
|
int addr = ((PPU.OAMAddr & 0x10f) << 1) + (PPU.OAMFlip & 1);
|
|
|
|
if (byte != PPU.OAMData [addr]){
|
|
|
|
FLUSH_REDRAW ();
|
|
|
|
PPU.OAMData [addr] = byte;
|
|
|
|
IPPU.OBJChanged = TRUE;
|
|
|
|
|
|
|
|
// X position high bit, and sprite size (x4)
|
|
|
|
struct SOBJ *pObj = &PPU.OBJ [(addr & 0x1f) * 4];
|
|
|
|
|
|
|
|
pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 0) & 1];
|
|
|
|
pObj++->Size = byte & 2;
|
|
|
|
pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 2) & 1];
|
|
|
|
pObj++->Size = byte & 8;
|
|
|
|
pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 4) & 1];
|
|
|
|
pObj++->Size = byte & 32;
|
|
|
|
pObj->HPos = (pObj->HPos & 0xFF) | SignExtend[(byte >> 6) & 1];
|
|
|
|
pObj->Size = byte & 128;
|
|
|
|
}
|
|
|
|
PPU.OAMFlip ^= 1;
|
|
|
|
if(!(PPU.OAMFlip & 1)){
|
|
|
|
++PPU.OAMAddr;
|
|
|
|
PPU.OAMAddr &= 0x1ff;
|
|
|
|
if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
|
|
|
|
{
|
|
|
|
PPU.FirstSprite = (PPU.OAMAddr&0xFE) >> 1;
|
|
|
|
IPPU.OBJChanged = TRUE;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (PPU.OAMPriorityRotation && (PPU.OAMAddr&1)) IPPU.OBJChanged = TRUE;
|
|
|
|
}
|
|
|
|
} else if(!(PPU.OAMFlip & 1)){
|
|
|
|
PPU.OAMWriteRegister &= 0xff00;
|
|
|
|
PPU.OAMWriteRegister |= byte;
|
|
|
|
PPU.OAMFlip |= 1;
|
|
|
|
if (PPU.OAMPriorityRotation && (PPU.OAMAddr&1)) IPPU.OBJChanged = TRUE;
|
|
|
|
} else {
|
|
|
|
PPU.OAMWriteRegister &= 0x00ff;
|
|
|
|
uint8 lowbyte = (uint8)(PPU.OAMWriteRegister);
|
|
|
|
uint8 highbyte = byte;
|
|
|
|
PPU.OAMWriteRegister |= byte << 8;
|
|
|
|
|
|
|
|
int addr = (PPU.OAMAddr << 1);
|
|
|
|
|
|
|
|
if (lowbyte != PPU.OAMData [addr] ||
|
|
|
|
highbyte != PPU.OAMData [addr+1])
|
|
|
|
{
|
|
|
|
FLUSH_REDRAW ();
|
|
|
|
PPU.OAMData [addr] = lowbyte;
|
|
|
|
PPU.OAMData [addr+1] = highbyte;
|
|
|
|
IPPU.OBJChanged = TRUE;
|
|
|
|
if (addr & 2)
|
|
|
|
{
|
|
|
|
// Tile
|
|
|
|
PPU.OBJ[addr = PPU.OAMAddr >> 1].Name = PPU.OAMWriteRegister & 0x1ff;
|
|
|
|
|
|
|
|
// priority, h and v flip.
|
|
|
|
PPU.OBJ[addr].Palette = (highbyte >> 1) & 7;
|
|
|
|
PPU.OBJ[addr].Priority = (highbyte >> 4) & 3;
|
|
|
|
PPU.OBJ[addr].HFlip = (highbyte >> 6) & 1;
|
|
|
|
PPU.OBJ[addr].VFlip = (highbyte >> 7) & 1;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
// X position (low)
|
|
|
|
PPU.OBJ[addr = PPU.OAMAddr >> 1].HPos &= 0xFF00;
|
|
|
|
PPU.OBJ[addr].HPos |= lowbyte;
|
|
|
|
|
|
|
|
// Sprite Y position
|
|
|
|
PPU.OBJ[addr].VPos = highbyte;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
PPU.OAMFlip &= ~1;
|
|
|
|
++PPU.OAMAddr;
|
|
|
|
if (PPU.OAMPriorityRotation && PPU.FirstSprite != (PPU.OAMAddr >> 1))
|
|
|
|
{
|
|
|
|
PPU.FirstSprite = (PPU.OAMAddr&0xFE) >> 1;
|
|
|
|
IPPU.OBJChanged = TRUE;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
Memory.FillRAM [0x2104] = byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2118 (uint8 Byte)
|
|
|
|
{
|
|
|
|
uint32 address;
|
|
|
|
if (PPU.VMA.FullGraphicCount)
|
|
|
|
{
|
|
|
|
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
|
|
|
address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) +
|
|
|
|
(rem >> PPU.VMA.Shift) +
|
|
|
|
((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
|
|
|
|
Memory.VRAM [address] = Byte;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xFFFF] = Byte;
|
|
|
|
}
|
|
|
|
IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
if (!PPU.VMA.High)
|
|
|
|
{
|
|
|
|
#ifdef DEBUGGER
|
2008-10-16 03:49:58 +02:00
|
|
|
if (Settings.TraceVRAM && !CPU.InDMA)
|
2008-08-06 03:09:59 +02:00
|
|
|
{
|
|
|
|
printf ("VRAM write byte: $%04X (%d,%d)\n", PPU.VMA.Address,
|
|
|
|
Memory.FillRAM[0x2115] & 3,
|
|
|
|
(Memory.FillRAM [0x2115] & 0x0c) >> 2);
|
|
|
|
}
|
2008-10-16 03:49:58 +02:00
|
|
|
#endif
|
2008-08-06 03:09:59 +02:00
|
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
|
|
}
|
|
|
|
// Memory.FillRAM [0x2118] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2118_tile (uint8 Byte)
|
|
|
|
{
|
|
|
|
uint32 address;
|
|
|
|
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
|
|
|
address = (((PPU.VMA.Address & ~PPU.VMA.Mask1) +
|
|
|
|
(rem >> PPU.VMA.Shift) +
|
|
|
|
((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) & 0xffff;
|
|
|
|
Memory.VRAM [address] = Byte;
|
|
|
|
IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
if (!PPU.VMA.High)
|
|
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
|
|
// Memory.FillRAM [0x2118] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2118_linear (uint8 Byte)
|
|
|
|
{
|
|
|
|
uint32 address;
|
|
|
|
Memory.VRAM[address = (PPU.VMA.Address << 1) & 0xFFFF] = Byte;
|
|
|
|
IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
if (!PPU.VMA.High)
|
|
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
|
|
// Memory.FillRAM [0x2118] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2119 (uint8 Byte)
|
|
|
|
{
|
|
|
|
uint32 address;
|
|
|
|
if (PPU.VMA.FullGraphicCount)
|
|
|
|
{
|
|
|
|
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
|
|
|
address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) +
|
|
|
|
(rem >> PPU.VMA.Shift) +
|
|
|
|
((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xFFFF;
|
|
|
|
Memory.VRAM [address] = Byte;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xFFFF] = Byte;
|
|
|
|
}
|
|
|
|
IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
if (PPU.VMA.High)
|
|
|
|
{
|
|
|
|
#ifdef DEBUGGER
|
2008-10-16 03:49:58 +02:00
|
|
|
if (Settings.TraceVRAM && !CPU.InDMA)
|
2008-08-06 03:09:59 +02:00
|
|
|
{
|
|
|
|
printf ("VRAM write word: $%04X (%d,%d)\n", PPU.VMA.Address,
|
|
|
|
Memory.FillRAM[0x2115] & 3,
|
|
|
|
(Memory.FillRAM [0x2115] & 0x0c) >> 2);
|
|
|
|
}
|
2008-10-16 03:49:58 +02:00
|
|
|
#endif
|
2008-08-06 03:09:59 +02:00
|
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
|
|
}
|
|
|
|
// Memory.FillRAM [0x2119] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2119_tile (uint8 Byte)
|
|
|
|
{
|
|
|
|
uint32 rem = PPU.VMA.Address & PPU.VMA.Mask1;
|
|
|
|
uint32 address = ((((PPU.VMA.Address & ~PPU.VMA.Mask1) +
|
|
|
|
(rem >> PPU.VMA.Shift) +
|
|
|
|
((rem & (PPU.VMA.FullGraphicCount - 1)) << 3)) << 1) + 1) & 0xFFFF;
|
|
|
|
Memory.VRAM [address] = Byte;
|
|
|
|
IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
if (PPU.VMA.High)
|
|
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
|
|
// Memory.FillRAM [0x2119] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2119_linear (uint8 Byte)
|
|
|
|
{
|
|
|
|
uint32 address;
|
|
|
|
Memory.VRAM[address = ((PPU.VMA.Address << 1) + 1) & 0xFFFF] = Byte;
|
|
|
|
IPPU.TileCached [TILE_2BIT][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_8BIT][address >> 6] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_EVEN][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][address >> 4] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_2BIT_ODD][((address >> 4)-1)&(MAX_2BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_EVEN][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][address >> 5] = FALSE;
|
|
|
|
IPPU.TileCached [TILE_4BIT_ODD][((address >> 5)-1)&(MAX_4BIT_TILES-1)] = FALSE;
|
|
|
|
if (PPU.VMA.High)
|
|
|
|
PPU.VMA.Address += PPU.VMA.Increment;
|
|
|
|
// Memory.FillRAM [0x2119] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2122(uint8 Byte)
|
|
|
|
{
|
|
|
|
// CG-RAM (palette) write
|
|
|
|
|
|
|
|
if (PPU.CGFLIP)
|
|
|
|
{
|
|
|
|
if ((Byte & 0x7f) != (PPU.CGDATA[PPU.CGADD] >> 8))
|
|
|
|
{
|
|
|
|
FLUSH_REDRAW ();
|
|
|
|
PPU.CGDATA[PPU.CGADD] &= 0x00FF;
|
|
|
|
PPU.CGDATA[PPU.CGADD] |= (Byte & 0x7f) << 8;
|
|
|
|
IPPU.ColorsChanged = TRUE;
|
|
|
|
IPPU.Blue [PPU.CGADD] = IPPU.XB [(Byte >> 2) & 0x1f];
|
|
|
|
IPPU.Green [PPU.CGADD] = IPPU.XB [(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
|
|
|
|
IPPU.ScreenColors [PPU.CGADD] = (uint16) BUILD_PIXEL (IPPU.Red [PPU.CGADD],
|
|
|
|
IPPU.Green [PPU.CGADD],
|
|
|
|
IPPU.Blue [PPU.CGADD]);
|
|
|
|
}
|
|
|
|
PPU.CGADD++;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (Byte != (uint8) (PPU.CGDATA[PPU.CGADD] & 0xff))
|
|
|
|
{
|
|
|
|
FLUSH_REDRAW ();
|
|
|
|
PPU.CGDATA[PPU.CGADD] &= 0x7F00;
|
|
|
|
PPU.CGDATA[PPU.CGADD] |= Byte;
|
|
|
|
IPPU.ColorsChanged = TRUE;
|
|
|
|
IPPU.Red [PPU.CGADD] = IPPU.XB [Byte & 0x1f];
|
|
|
|
IPPU.Green [PPU.CGADD] = IPPU.XB [(PPU.CGDATA[PPU.CGADD] >> 5) & 0x1f];
|
|
|
|
IPPU.ScreenColors [PPU.CGADD] = (uint16) BUILD_PIXEL (IPPU.Red [PPU.CGADD],
|
|
|
|
IPPU.Green [PPU.CGADD],
|
|
|
|
IPPU.Blue [PPU.CGADD]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
PPU.CGFLIP ^= 1;
|
|
|
|
// Memory.FillRAM [0x2122] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC inline void REGISTER_2180(uint8 Byte)
|
|
|
|
{
|
|
|
|
Memory.RAM[PPU.WRAM++] = Byte;
|
|
|
|
PPU.WRAM &= 0x1FFFF;
|
|
|
|
Memory.FillRAM [0x2180] = Byte;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|