mirror of
https://github.com/dborth/snes9xgx.git
synced 2024-11-01 16:35:16 +01:00
853 lines
18 KiB
C++
853 lines
18 KiB
C++
// SPC emulation support: init, sample buffering, reset, SPC loading
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// snes_spc 0.9.0. http://www.slack.net/~ant/
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#include "SNES_SPC.h"
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#include <string.h>
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/* Copyright (C) 2004-2007 Shay Green. This module is free software; you
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can redistribute it and/or modify it under the terms of the GNU Lesser
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General Public License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version. This
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module is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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details. You should have received a copy of the GNU Lesser General Public
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License along with this module; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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#include "blargg_source.h"
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#define RAM (m.ram.ram)
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#define REGS (m.smp_regs [0])
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#define REGS_IN (m.smp_regs [1])
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// (n ? n : 256)
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#define IF_0_THEN_256( n ) ((uint8_t) ((n) - 1) + 1)
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//// Init
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blargg_err_t SNES_SPC::init()
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{
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memset( &m, 0, sizeof m );
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dsp.init( RAM );
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m.tempo = tempo_unit;
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// Most SPC music doesn't need ROM, and almost all the rest only rely
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// on these two bytes
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m.rom [0x3E] = 0xFF;
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m.rom [0x3F] = 0xC0;
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static unsigned char const cycle_table [128] =
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{// 01 23 45 67 89 AB CD EF
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0x28,0x47,0x34,0x36,0x26,0x54,0x54,0x68, // 0
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0x48,0x47,0x45,0x56,0x55,0x65,0x22,0x46, // 1
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0x28,0x47,0x34,0x36,0x26,0x54,0x54,0x74, // 2
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0x48,0x47,0x45,0x56,0x55,0x65,0x22,0x38, // 3
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0x28,0x47,0x34,0x36,0x26,0x44,0x54,0x66, // 4
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0x48,0x47,0x45,0x56,0x55,0x45,0x22,0x43, // 5
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0x28,0x47,0x34,0x36,0x26,0x44,0x54,0x75, // 6
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0x48,0x47,0x45,0x56,0x55,0x55,0x22,0x36, // 7
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0x28,0x47,0x34,0x36,0x26,0x54,0x52,0x45, // 8
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0x48,0x47,0x45,0x56,0x55,0x55,0x22,0xC5, // 9
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0x38,0x47,0x34,0x36,0x26,0x44,0x52,0x44, // A
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0x48,0x47,0x45,0x56,0x55,0x55,0x22,0x34, // B
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0x38,0x47,0x45,0x47,0x25,0x64,0x52,0x49, // C
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0x48,0x47,0x56,0x67,0x45,0x55,0x22,0x83, // D
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0x28,0x47,0x34,0x36,0x24,0x53,0x43,0x40, // E
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0x48,0x47,0x45,0x56,0x34,0x54,0x22,0x60, // F
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};
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// unpack cycle table
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for ( int i = 0; i < 128; i++ )
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{
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int n = cycle_table [i];
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m.cycle_table [i * 2 + 0] = n >> 4;
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m.cycle_table [i * 2 + 1] = n & 0x0F;
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}
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allow_time_overflow = false;
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dsp.rom = m.rom;
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dsp.hi_ram = m.hi_ram;
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#ifdef DEBUGGER
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apu_trace = NULL;
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debug_trace = false;
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#endif
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#if SPC_LESS_ACCURATE
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memcpy( reg_times, reg_times_, sizeof reg_times );
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#endif
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reset();
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return 0;
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}
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void SNES_SPC::init_rom( uint8_t const in [rom_size] )
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{
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memcpy( m.rom, in, sizeof m.rom );
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}
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void SNES_SPC::set_tempo( int t )
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{
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m.tempo = t;
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int const timer2_shift = 4; // 64 kHz
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int const other_shift = 3; // 8 kHz
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#if SPC_DISABLE_TEMPO
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m.timers [2].prescaler = timer2_shift;
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m.timers [1].prescaler = timer2_shift + other_shift;
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m.timers [0].prescaler = timer2_shift + other_shift;
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#else
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if ( !t )
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t = 1;
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int const timer2_rate = 1 << timer2_shift;
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int rate = (timer2_rate * tempo_unit + (t >> 1)) / t;
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if ( rate < timer2_rate / 4 )
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rate = timer2_rate / 4; // max 4x tempo
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m.timers [2].prescaler = rate;
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m.timers [1].prescaler = rate << other_shift;
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m.timers [0].prescaler = rate << other_shift;
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#endif
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}
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// Timer registers have been loaded. Applies these to the timers. Does not
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// reset timer prescalers or dividers.
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void SNES_SPC::timers_loaded()
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{
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int i;
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for ( i = 0; i < timer_count; i++ )
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{
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Timer* t = &m.timers [i];
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t->period = IF_0_THEN_256( REGS [r_t0target + i] );
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t->enabled = REGS [r_control] >> i & 1;
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t->counter = REGS_IN [r_t0out + i] & 0x0F;
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}
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set_tempo( m.tempo );
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}
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// Loads registers from unified 16-byte format
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void SNES_SPC::load_regs( uint8_t const in [reg_count] )
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{
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memcpy( REGS, in, reg_count );
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memcpy( REGS_IN, REGS, reg_count );
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// These always read back as 0
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REGS_IN [r_test ] = 0;
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REGS_IN [r_control ] = 0;
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REGS_IN [r_t0target] = 0;
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REGS_IN [r_t1target] = 0;
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REGS_IN [r_t2target] = 0;
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}
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// RAM was just loaded from SPC, with $F0-$FF containing SMP registers
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// and timer counts. Copies these to proper registers.
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void SNES_SPC::ram_loaded()
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{
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m.rom_enabled = dsp.rom_enabled = 0;
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load_regs( &RAM [0xF0] );
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// Put STOP instruction around memory to catch PC underflow/overflow
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memset( m.ram.padding1, cpu_pad_fill, sizeof m.ram.padding1 );
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memset( m.ram.padding2, cpu_pad_fill, sizeof m.ram.padding2 );
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}
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// Registers were just loaded. Applies these new values.
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void SNES_SPC::regs_loaded()
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{
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enable_rom( REGS [r_control] & 0x80 );
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timers_loaded();
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}
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void SNES_SPC::reset_time_regs()
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{
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m.cpu_error = 0;
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m.echo_accessed = 0;
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m.spc_time = 0;
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m.dsp_time = 0;
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#if SPC_LESS_ACCURATE
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m.dsp_time = clocks_per_sample + 1;
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#endif
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for ( int i = 0; i < timer_count; i++ )
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{
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Timer* t = &m.timers [i];
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t->next_time = 1;
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t->divider = 0;
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}
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regs_loaded();
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m.extra_clocks = 0;
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reset_buf();
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}
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void SNES_SPC::reset_common( int timer_counter_init )
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{
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int i;
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for ( i = 0; i < timer_count; i++ )
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REGS_IN [r_t0out + i] = timer_counter_init;
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// Run IPL ROM
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memset( &m.cpu_regs, 0, sizeof m.cpu_regs );
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m.cpu_regs.pc = rom_addr;
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REGS [r_test ] = 0x0A;
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REGS [r_control] = 0xB0; // ROM enabled, clear ports
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for ( i = 0; i < port_count; i++ )
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REGS_IN [r_cpuio0 + i] = 0;
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reset_time_regs();
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}
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void SNES_SPC::soft_reset()
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{
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reset_common( 0 );
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dsp.soft_reset();
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}
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void SNES_SPC::reset()
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{
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m.cpu_regs.pc = 0xFFC0;
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m.cpu_regs.a = 0x00;
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m.cpu_regs.x = 0x00;
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m.cpu_regs.y = 0x00;
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m.cpu_regs.psw = 0x02;
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m.cpu_regs.sp = 0xEF;
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memset( RAM, 0x00, 0x10000 );
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ram_loaded();
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reset_common( 0x0F );
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dsp.reset();
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}
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char const SNES_SPC::signature [signature_size + 1] =
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"SNES-SPC700 Sound File Data v0.30\x1A\x1A";
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blargg_err_t SNES_SPC::load_spc( void const* data, long size )
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{
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spc_file_t const* const spc = (spc_file_t const*) data;
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// be sure compiler didn't insert any padding into fle_t
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assert( sizeof (spc_file_t) == spc_min_file_size + 0x80 );
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// Check signature and file size
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if ( size < signature_size || memcmp( spc, signature, 27 ) )
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return "Not an SPC file";
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if ( size < spc_min_file_size )
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return "Corrupt SPC file";
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// CPU registers
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m.cpu_regs.pc = spc->pch * 0x100 + spc->pcl;
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m.cpu_regs.a = spc->a;
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m.cpu_regs.x = spc->x;
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m.cpu_regs.y = spc->y;
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m.cpu_regs.psw = spc->psw;
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m.cpu_regs.sp = spc->sp;
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// RAM and registers
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memcpy( RAM, spc->ram, 0x10000 );
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ram_loaded();
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// DSP registers
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dsp.load( spc->dsp );
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reset_time_regs();
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return 0;
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}
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void SNES_SPC::clear_echo()
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{
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if ( !(dsp.read( SPC_DSP::r_flg ) & 0x20) )
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{
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int addr = 0x100 * dsp.read( SPC_DSP::r_esa );
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int end = addr + 0x800 * (dsp.read( SPC_DSP::r_edl ) & 0x0F);
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if ( end > 0x10000 )
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end = 0x10000;
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memset( &RAM [addr], 0xFF, end - addr );
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}
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}
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//// Sample output
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void SNES_SPC::reset_buf()
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{
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// Start with half extra buffer of silence
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sample_t* out = m.extra_buf;
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while ( out < &m.extra_buf [extra_size / 2] )
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*out++ = 0;
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m.extra_pos = out;
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m.buf_begin = 0;
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dsp.set_output( 0, 0 );
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}
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void SNES_SPC::set_output( sample_t* out, int size )
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{
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m.extra_clocks &= clocks_per_sample - 1;
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if ( out )
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{
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sample_t const* out_end = out + size;
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m.buf_begin = out;
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m.buf_end = out_end;
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// Copy extra to output
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sample_t const* in = m.extra_buf;
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while ( in < m.extra_pos && out < out_end )
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*out++ = *in++;
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// Handle output being full already
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if ( out >= out_end )
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{
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// Have DSP write to remaining extra space
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out = dsp.extra();
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out_end = &dsp.extra() [extra_size];
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// Copy any remaining extra samples as if DSP wrote them
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while ( in < m.extra_pos )
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*out++ = *in++;
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assert( out <= out_end );
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}
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dsp.set_output( out, out_end - out );
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}
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else
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{
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reset_buf();
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}
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}
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void SNES_SPC::save_extra()
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{
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// Get end pointers
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sample_t const* main_end = m.buf_end; // end of data written to buf
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sample_t const* dsp_end = dsp.out_pos(); // end of data written to dsp.extra()
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if ( m.buf_begin <= dsp_end && dsp_end <= main_end )
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{
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main_end = dsp_end;
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dsp_end = dsp.extra(); // nothing in DSP's extra
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}
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// Copy any extra samples at these ends into extra_buf
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sample_t* out = m.extra_buf;
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sample_t const* in;
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for ( in = m.buf_begin + sample_count(); in < main_end; in++ )
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*out++ = *in;
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for ( in = dsp.extra(); in < dsp_end ; in++ )
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*out++ = *in;
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m.extra_pos = out;
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assert( out <= &m.extra_buf [extra_size] );
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}
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blargg_err_t SNES_SPC::play( int count, sample_t* out )
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{
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if ( count )
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{
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set_output( out, count );
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end_frame( count * (clocks_per_sample / 2) );
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}
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const char* err = m.cpu_error;
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m.cpu_error = 0;
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return err;
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}
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blargg_err_t SNES_SPC::skip( int count )
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{
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#if SPC_LESS_ACCURATE
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if ( count > 2 * sample_rate * 2 )
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{
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set_output( 0, 0 );
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// Skip a multiple of 4 samples
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time_t end = count;
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count = (count & 3) + 1 * sample_rate * 2;
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end = (end - count) * (clocks_per_sample / 2);
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m.skipped_kon = 0;
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m.skipped_koff = 0;
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// Preserve DSP and timer synchronization
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// TODO: verify that this really preserves it
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int old_dsp_time = m.dsp_time + m.spc_time;
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m.dsp_time = end - m.spc_time + skipping_time;
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end_frame( end );
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m.dsp_time = m.dsp_time - skipping_time + old_dsp_time;
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dsp.write( SPC_DSP::r_koff, m.skipped_koff & ~m.skipped_kon );
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dsp.write( SPC_DSP::r_kon , m.skipped_kon );
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clear_echo();
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}
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#endif
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return play( count, 0 );
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}
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//// Snes9x Accessor
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void SNES_SPC::dsp_set_spc_snapshot_callback( void (*callback) (void) )
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{
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dsp.set_spc_snapshot_callback( callback );
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}
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void SNES_SPC::dsp_dump_spc_snapshot( void )
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{
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dsp.dump_spc_snapshot();
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}
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void SNES_SPC::dsp_set_stereo_switch( int value )
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{
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dsp.set_stereo_switch( value );
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}
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SNES_SPC::uint8_t SNES_SPC::dsp_reg_value( int ch, int addr )
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{
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return dsp.reg_value( ch, addr );
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}
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int SNES_SPC::dsp_envx_value( int ch )
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{
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return dsp.envx_value( ch );
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}
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//// Snes9x debugger
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#ifdef DEBUGGER
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void SNES_SPC::debug_toggle_trace( void )
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{
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debug_trace = !debug_trace;
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if (debug_trace)
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{
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printf("APU tracing enabled.\n");
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ENSURE_TRACE_OPEN(apu_trace, "apu_trace.log", "wb")
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}
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else
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{
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printf("APU tracing disabled.\n");
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fclose(apu_trace);
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apu_trace = NULL;
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}
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}
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bool SNES_SPC::debug_is_enabled( void ) { return debug_trace; }
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void SNES_SPC::debug_do_trace( int a, int x, int y, uint8_t const *pc, uint8_t *sp, int psw, int c, int nz, int dp )
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{
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char msg[512];
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ENSURE_TRACE_OPEN(apu_trace, "apu_trace.log", "a")
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debug_op_print(msg, a, x, y, pc, sp, psw, c, nz, dp);
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fprintf(apu_trace, "%s ", msg);
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debug_io_print(msg);
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fprintf(apu_trace, "%s ", msg);
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S9xPrintHVPosition(msg);
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fprintf(apu_trace, "%s\n", msg);
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}
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void SNES_SPC::debug_op_print( char *buffer, int a, int x, int y, uint8_t const *pc, uint8_t *sp, int psw, int c, int nz, int dp )
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{
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static char mnemonics[256][20] =
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{
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"NOP",
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"TCALL 0",
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"SET1 $%02X.0",
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"BBS $%02X.0,$%04X",
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"OR A,$%02X",
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"OR A,!$%04X",
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"OR A,(X)",
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"OR A,[$%02X+X]",
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"OR A,#$%02X",
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"OR $%02X,$%02X",
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"OR1 C,$%04X.%d",
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"ASL $%02X",
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"MOV !$%04X,Y",
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"PUSH PSW",
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"TSET1 !$%04X",
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"BRK",
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"BPL $%04X",
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"TCALL 1",
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"CLR1 $%02X.0",
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"BBC $%02X.0,$%04X",
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"OR A,$%02X+X",
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"OR A,!$%04X+X",
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"OR A,!$%04X+Y",
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"OR A,[$%02X]+Y",
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"OR $%02X,#$%02X",
|
|
"OR (X),(Y)",
|
|
"DECW $%02X",
|
|
"ASL $%02X+X",
|
|
"ASL A",
|
|
"DEC X",
|
|
"CMP X,!$%04X",
|
|
"JMP [!$%04X+X]",
|
|
"CLRP",
|
|
"TCALL 2",
|
|
"SET1 $%02X.1",
|
|
"BBS $%02X.1,$%04X",
|
|
"AND A,$%02X",
|
|
"AND A,!$%04X",
|
|
"AND A,(X)",
|
|
"AND A,[$%02X+X]",
|
|
"AND A,#$%02X",
|
|
"AND $%02X,$%02X",
|
|
"OR1 C,/$%04X.%d",
|
|
"ROL $%02X",
|
|
"ROL !$%04X",
|
|
"PUSH A",
|
|
"CBNE $%02X,$%04X",
|
|
"BRA $%04X",
|
|
"BMI $%04X",
|
|
"TCALL 3",
|
|
"CLR1 $%02X.1",
|
|
"BBC $%02X.1,$%04X",
|
|
"AND A,$%02X+X",
|
|
"AND A,!$%04X+X",
|
|
"AND A,!$%04X+Y",
|
|
"AND A,[$%02X]+Y",
|
|
"AND $%02X,#$%02X",
|
|
"AND (X),(Y)",
|
|
"INCW $%02X",
|
|
"ROL $%02X+X",
|
|
"ROL A",
|
|
"INC X",
|
|
"CMP X,$%02X",
|
|
"CALL !$%04X",
|
|
"SETP",
|
|
"TCALL 4",
|
|
"SET1 $%02X.2",
|
|
"BBS $%02X.2,$%04X",
|
|
"EOR A,$%02X",
|
|
"EOR A,!$%04X",
|
|
"EOR A,(X)",
|
|
"EOR A,[$%02X+X]",
|
|
"EOR A,#$%02X",
|
|
"EOR $%02X,$%02X",
|
|
"AND1 C,$%04X.%d",
|
|
"LSR $%02X",
|
|
"LSR !$%04X",
|
|
"PUSH X",
|
|
"TCLR1 !$%04X",
|
|
"PCALL $%02X",
|
|
"BVC $%04X",
|
|
"TCALL 5",
|
|
"CLR1 $%02X.2",
|
|
"BBC $%02X.2,$%04X",
|
|
"EOR A,$%02X+X",
|
|
"EOR A,!$%04X+X",
|
|
"EOR A,!$%04X+Y",
|
|
"EOR A,[$%02X]+Y",
|
|
"EOR $%02X,#$%02X",
|
|
"EOR (X),(Y)",
|
|
"CMPW YA,$%02X",
|
|
"LSR $%02X+X",
|
|
"LSR A",
|
|
"MOV X,A",
|
|
"CMP Y,!$%04X",
|
|
"JMP !$%04X",
|
|
"CLRC",
|
|
"TCALL 6",
|
|
"SET1 $%02X.3",
|
|
"BBS $%02X.3,$%04X",
|
|
"CMP A,$%02X",
|
|
"CMP A,!$%04X",
|
|
"CMP A,(X)",
|
|
"CMP A,[$%02X+X]",
|
|
"CMP A,#$%02X",
|
|
"CMP $%02X,$%02X",
|
|
"AND1 C,/$%04X.%d",
|
|
"ROR $%02X",
|
|
"ROR !$%04X",
|
|
"PUSH Y",
|
|
"DBNZ $%02X,$%04X",
|
|
"RET",
|
|
"BVS $%04X",
|
|
"TCALL 7",
|
|
"CLR1 $%02X.3",
|
|
"BBC $%02X.3,$%04X",
|
|
"CMP A,$%02X+X",
|
|
"CMP A,!$%04X+X",
|
|
"CMP A,!$%04X+Y",
|
|
"CMP A,[$%02X]+Y",
|
|
"CMP $%02X,#$%02X",
|
|
"CMP (X),(Y)",
|
|
"ADDW YA,$%02X",
|
|
"ROR $%02X+X",
|
|
"ROR A",
|
|
"MOV A,X",
|
|
"CMP Y,$%02X",
|
|
"RET1",
|
|
"SETC",
|
|
"TCALL 8",
|
|
"SET1 $%02X.4",
|
|
"BBS $%02X.4,$%04X",
|
|
"ADC A,$%02X",
|
|
"ADC A,!$%04X",
|
|
"ADC A,(X)",
|
|
"ADC A,[$%02X+X]",
|
|
"ADC A,#$%02X",
|
|
"ADC $%02X,$%02X",
|
|
"EOR1 C,$%04X.%d",
|
|
"DEC $%02X",
|
|
"DEC !$%04X",
|
|
"MOV Y,#$%02X",
|
|
"POP PSW",
|
|
"MOV $%02X,#$%02X",
|
|
"BCC $%04X",
|
|
"TCALL 9",
|
|
"CLR1 $%02X.4",
|
|
"BBC $%02X.4,$%04X",
|
|
"ADC A,$%02X+X",
|
|
"ADC A,!$%04X+X",
|
|
"ADC A,!$%04X+Y",
|
|
"ADC A,[$%02X]+Y",
|
|
"ADC $%02X,#$%02X",
|
|
"ADC (X),(Y)",
|
|
"SUBW YA,$%02X",
|
|
"DEC $%02X+X",
|
|
"DEC A",
|
|
"MOV X,SP",
|
|
"DIV YA,X",
|
|
"XCN A",
|
|
"EI",
|
|
"TCALL 10",
|
|
"SET1 $%02X.5",
|
|
"BBS $%02X.5,$%04X",
|
|
"SBC A,$%02X",
|
|
"SBC A,!$%04X",
|
|
"SBC A,(X)",
|
|
"SBC A,[$%02X+X]",
|
|
"SBC A,#$%02X",
|
|
"SBC $%02X,$%02X",
|
|
"MOV1 C,$%04X.%d",
|
|
"INC $%02X",
|
|
"INC !$%04X",
|
|
"CMP Y,#$%02X",
|
|
"POP A",
|
|
"MOV (X)+,A",
|
|
"BCS $%04X",
|
|
"TCALL 11",
|
|
"CLR1 $%02X.5",
|
|
"BBC $%02X.5,$%04X",
|
|
"SBC A,$%02X+X",
|
|
"SBC A,!$%04X+X",
|
|
"SBC A,!$%04X+Y",
|
|
"SBC A,[$%02X]+Y",
|
|
"SBC $%02X,#$%02X",
|
|
"SBC (X),(Y)",
|
|
"MOVW YA,$%02X",
|
|
"INC $%02X+X",
|
|
"INC A",
|
|
"MOV SP,X",
|
|
"DAS A",
|
|
"MOV A,(X)+",
|
|
"DI",
|
|
"TCALL 12",
|
|
"SET1 $%02X.6",
|
|
"BBS $%02X.6,$%04X",
|
|
"MOV $%02X,A",
|
|
"MOV !$%04X,A",
|
|
"MOV (X),A",
|
|
"MOV [$%02X+X],A",
|
|
"CMP X,#$%02X",
|
|
"MOV !$%04X,X",
|
|
"MOV1 $%04X.%d,C",
|
|
"MOV $%02X,Y",
|
|
"ASL !$%04X",
|
|
"MOV X,#$%02X",
|
|
"POP X",
|
|
"MUL YA",
|
|
"BNE $%04X",
|
|
"TCALL 13",
|
|
"CLR1 $%02X.6",
|
|
"BBC $%02X.6,$%04X",
|
|
"MOV $%02X+X,A",
|
|
"MOV !$%04X+X,A",
|
|
"MOV !$%04X+Y,A",
|
|
"MOV [$%02X]+Y,A",
|
|
"MOV $%02X,X",
|
|
"MOV $%02X+Y,X",
|
|
"MOVW $%02X,YA",
|
|
"MOV $%02X+X,Y",
|
|
"DEC Y",
|
|
"MOV A,Y",
|
|
"CBNE $%02X+X,$%04X",
|
|
"DAA A",
|
|
"CLRV",
|
|
"TCALL 14",
|
|
"SET1 $%02X.7",
|
|
"BBS $%02X.7,$%04X",
|
|
"MOV A,$%02X",
|
|
"MOV A,!$%04X",
|
|
"MOV A,(X)",
|
|
"MOV A,[$%02X+X]",
|
|
"MOV A,#$%02X",
|
|
"MOV X,!$%04X",
|
|
"NOT1 $%04X.%d",
|
|
"MOV Y,$%02X",
|
|
"MOV Y,!$%04X",
|
|
"NOTC",
|
|
"POP Y",
|
|
"SLEEP",
|
|
"BEQ $%04X",
|
|
"TCALL 15",
|
|
"CLR1 $%02X.7",
|
|
"BBC $%02X.7,$%04X",
|
|
"MOV A,$%02X+X",
|
|
"MOV A,!$%04X+X",
|
|
"MOV A,!$%04X+Y",
|
|
"MOV A,[$%02X]+Y",
|
|
"MOV X,$%02X",
|
|
"MOV X,$%02X+Y",
|
|
"MOV $%02X,$%02X",
|
|
"MOV Y,$%02X+X",
|
|
"INC Y",
|
|
"MOV Y,A",
|
|
"DBNZ Y,$%04X",
|
|
"STOP"
|
|
};
|
|
|
|
static int modes[256] =
|
|
{
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 3, 6, 0, 1, 2, 1, 2,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 4, 2, 0, 0, 2, 2, 1, 1,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 3, 6, 0, 1, 2, 5, 7,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 4, 2, 0, 0, 2, 2, 0, 1,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 3, 6, 0, 1, 2, 1, 0,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 4, 2, 0, 0, 2, 2, 1, 1,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 3, 6, 0, 1, 2, 5, 2,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 4, 2, 0, 0, 2, 2, 0, 2,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 3, 6, 0, 1, 0, 2, 4,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 4, 2, 0, 0, 2, 2, 2, 2,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 3, 6, 0, 1, 0, 2, 2,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 4, 2, 0, 0, 2, 2, 2, 2,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 1, 6, 0, 1, 0, 2, 2,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 0, 0, 0, 0, 2, 2, 5, 2,
|
|
2, 2, 0, 5, 0, 1, 2, 0, 0, 1, 6, 0, 1, 2, 2, 2,
|
|
7, 2, 0, 5, 0, 1, 1, 0, 0, 0, 3, 0, 2, 2, 7, 2
|
|
};
|
|
|
|
static int modesToBytes[] =
|
|
{
|
|
2, 3, 1, 3, 3, 3, 3, 2
|
|
};
|
|
|
|
int const n80 = 0x80; // nz
|
|
int const p20 = 0x20; // dp
|
|
int const z02 = 0x02; // nz
|
|
int const c01 = 0x01; // c
|
|
|
|
#define GET_PC() (pc - ram)
|
|
#define GET_SP() (sp - 0x101 - ram)
|
|
#define GET_PSW( out )\
|
|
{\
|
|
out = psw & ~(n80 | p20 | z02 | c01);\
|
|
out |= c >> 8 & c01;\
|
|
out |= dp >> 3 & p20;\
|
|
out |= ((nz >> 4) | nz) & n80;\
|
|
if ( !(uint8_t) nz ) out |= z02;\
|
|
}
|
|
|
|
uint8_t const *ram = RAM;
|
|
|
|
int addr;
|
|
int tsp, tpsw;
|
|
uint8_t d0, d1, d2;
|
|
|
|
addr = GET_PC();
|
|
tsp = GET_SP();
|
|
GET_PSW(tpsw);
|
|
|
|
d0 = *pc;
|
|
d1 = (addr < 0xffff) ? *(pc + 1) : 0;
|
|
d2 = (addr < 0xfffe) ? *(pc + 2) : 0;
|
|
|
|
int mode = modes[d0];
|
|
int bytes = modesToBytes[mode];
|
|
char mnem[100];
|
|
|
|
switch (bytes)
|
|
{
|
|
case 1:
|
|
sprintf(buffer, "%04X %02X ", addr, d0);
|
|
break;
|
|
|
|
case 2:
|
|
sprintf(buffer, "%04X %02X %02X ", addr, d0, d1);
|
|
break;
|
|
|
|
case 3:
|
|
sprintf(buffer, "%04X %02X %02X %02X ", addr, d0, d1, d2);
|
|
break;
|
|
}
|
|
|
|
switch (mode)
|
|
{
|
|
case 0:
|
|
sprintf(mnem, mnemonics[d0], d1);
|
|
break;
|
|
|
|
case 1:
|
|
sprintf(mnem, mnemonics[d0], d1 + (d2 << 8));
|
|
break;
|
|
|
|
case 2:
|
|
strcpy (mnem, mnemonics[d0]);
|
|
break;
|
|
|
|
case 3:
|
|
sprintf(mnem, mnemonics[d0], d2, d1);
|
|
break;
|
|
|
|
case 4:
|
|
sprintf(mnem, mnemonics[d0], d2, d1);
|
|
break;
|
|
|
|
case 5:
|
|
sprintf(mnem, mnemonics[d0], d1, addr + 3 + (int8_t) d2);
|
|
break;
|
|
|
|
case 6:
|
|
sprintf(mnem, mnemonics[d0], (d1 + (d2 << 8)) & 0x1fff, d2 >> 5);
|
|
break;
|
|
|
|
case 7:
|
|
sprintf(mnem, mnemonics[d0], addr + 2 + (int8_t) d1);
|
|
break;
|
|
}
|
|
|
|
sprintf(buffer, "%s %-20s A:%02X X:%02X Y:%02X S:%02X P:%c%c%c%c%c%c%c%c ROM:%d",
|
|
buffer, mnem, a, x, y, tsp,
|
|
(tpsw & 0x80) ? 'N' : 'n',
|
|
(tpsw & 0x40) ? 'V' : 'v',
|
|
(tpsw & 0x20) ? 'P' : 'p',
|
|
(tpsw & 0x10) ? 'B' : 'b',
|
|
(tpsw & 0x08) ? 'H' : 'h',
|
|
(tpsw & 0x04) ? 'I' : 'i',
|
|
(tpsw & 0x02) ? 'Z' : 'z',
|
|
(tpsw & 0x01) ? 'C' : 'c',
|
|
m.rom_enabled ? 1 : 0);
|
|
}
|
|
|
|
void SNES_SPC::debug_io_print( char *buffer )
|
|
{
|
|
sprintf(buffer, "i/o %02X/%02X %02X/%02X %02X/%02X %02X/%02X",
|
|
m.smp_regs[1][r_cpuio0], m.smp_regs[0][r_cpuio0],
|
|
m.smp_regs[1][r_cpuio1], m.smp_regs[0][r_cpuio1],
|
|
m.smp_regs[1][r_cpuio2], m.smp_regs[0][r_cpuio2],
|
|
m.smp_regs[1][r_cpuio3], m.smp_regs[0][r_cpuio3]);
|
|
}
|
|
|
|
#endif
|