mirror of
https://github.com/dborth/snes9xgx.git
synced 2024-12-05 00:44:19 +01:00
65984b9102
- added: option to disable AA filtering
(snes graphics 'crisper', AA now default OFF)
- added: mapped zooming and turbo mode to classic controller
- added: preliminary usb support (loading)
- changed: sram and freezes now saved by filename, not internal romname.
If you have multiple versions of the same game, you can now have
srams and freezes for each version. A prompt to convert to the
new naming is provided for sram only.
- changed: by default, autoload/save sram and freeze enabled
784 lines
19 KiB
C++
784 lines
19 KiB
C++
/**********************************************************************************
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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(c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and
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Jerremy Koot (jkoot@snes9x.com)
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(c) Copyright 2002 - 2004 Matthew Kendora
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(c) Copyright 2002 - 2005 Peter Bortas (peter@bortas.org)
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(c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/)
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(c) Copyright 2001 - 2006 John Weidman (jweidman@slip.net)
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(c) Copyright 2002 - 2006 Brad Jorsch (anomie@users.sourceforge.net),
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funkyass (funkyass@spam.shaw.ca),
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Kris Bleakley (codeviolation@hotmail.com),
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Nach (n-a-c-h@users.sourceforge.net), and
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zones (kasumitokoduck@yahoo.com)
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BS-X C emulator code
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(c) Copyright 2005 - 2006 Dreamer Nom,
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zones
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C4 x86 assembler and some C emulation code
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(c) Copyright 2000 - 2003 _Demo_ (_demo_@zsnes.com),
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Nach,
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zsKnight (zsknight@zsnes.com)
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C4 C++ code
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(c) Copyright 2003 - 2006 Brad Jorsch,
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Nach
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DSP-1 emulator code
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(c) Copyright 1998 - 2006 _Demo_,
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Andreas Naive (andreasnaive@gmail.com)
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Gary Henderson,
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Ivar (ivar@snes9x.com),
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John Weidman,
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Kris Bleakley,
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Matthew Kendora,
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Nach,
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neviksti (neviksti@hotmail.com)
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DSP-2 emulator code
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(c) Copyright 2003 John Weidman,
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Kris Bleakley,
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Lord Nightmare (lord_nightmare@users.sourceforge.net),
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Matthew Kendora,
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neviksti
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DSP-3 emulator code
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(c) Copyright 2003 - 2006 John Weidman,
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Kris Bleakley,
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Lancer,
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z80 gaiden
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DSP-4 emulator code
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(c) Copyright 2004 - 2006 Dreamer Nom,
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John Weidman,
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Kris Bleakley,
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Nach,
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z80 gaiden
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OBC1 emulator code
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(c) Copyright 2001 - 2004 zsKnight,
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pagefault (pagefault@zsnes.com),
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Kris Bleakley,
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Ported from x86 assembler to C by sanmaiwashi
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SPC7110 and RTC C++ emulator code
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(c) Copyright 2002 Matthew Kendora with research by
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zsKnight,
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John Weidman,
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Dark Force
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S-DD1 C emulator code
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(c) Copyright 2003 Brad Jorsch with research by
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Andreas Naive,
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John Weidman
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S-RTC C emulator code
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(c) Copyright 2001-2006 byuu,
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John Weidman
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ST010 C++ emulator code
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(c) Copyright 2003 Feather,
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John Weidman,
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Kris Bleakley,
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Matthew Kendora
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Super FX x86 assembler emulator code
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(c) Copyright 1998 - 2003 _Demo_,
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pagefault,
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zsKnight,
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Super FX C emulator code
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(c) Copyright 1997 - 1999 Ivar,
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Gary Henderson,
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John Weidman
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Sound DSP emulator code is derived from SNEeSe and OpenSPC:
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(c) Copyright 1998 - 2003 Brad Martin
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(c) Copyright 1998 - 2006 Charles Bilyue'
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SH assembler code partly based on x86 assembler code
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(c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se)
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2xSaI filter
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(c) Copyright 1999 - 2001 Derek Liauw Kie Fa
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HQ2x filter
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(c) Copyright 2003 Maxim Stepin (maxim@hiend3d.com)
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Specific ports contains the works of other authors. See headers in
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individual files.
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Snes9x homepage: http://www.snes9x.com
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Permission to use, copy, modify and/or distribute Snes9x in both binary
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and source form, for non-commercial purposes, is hereby granted without
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fee, providing that this license information and copyright notice appear
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with all copies and any derived work.
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This software is provided 'as-is', without any express or implied
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warranty. In no event shall the authors be held liable for any damages
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arising from the use of this software or it's derivatives.
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Snes9x is freeware for PERSONAL USE only. Commercial users should
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seek permission of the copyright holders first. Commercial use includes,
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but is not limited to, charging money for Snes9x or software derived from
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Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
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using Snes9x as a promotion for your commercial product.
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The copyright holders request that bug fixes and improvements to the code
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should be forwarded to them so everyone can benefit from the modifications
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in future versions.
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Super NES and Super Nintendo Entertainment System are trademarks of
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Nintendo Co., Limited and its subsidiary companies.
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**********************************************************************************/
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#include "fxemu.h"
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#include "fxinst.h"
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#include <stdlib.h>
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#include <string.h>
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#include <stdio.h>
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/* The FxChip Emulator's internal variables */
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struct FxRegs_s GSU = FxRegs_s_null;
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uint32 (**fx_ppfFunctionTable)(uint32) = 0;
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void (**fx_ppfPlotTable)() = 0;
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void (**fx_ppfOpcodeTable)() = 0;
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#if 0
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void fx_setCache()
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{
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uint32 c;
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GSU.bCacheActive = TRUE;
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GSU.pvRegisters[0x3e] &= 0xf0;
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c = (uint32)GSU.pvRegisters[0x3e];
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c |= ((uint32)GSU.pvRegisters[0x3f])<<8;
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if(c == GSU.vCacheBaseReg)
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return;
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GSU.vCacheBaseReg = c;
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GSU.vCacheFlags = 0;
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if(c < (0x10000-512))
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{
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uint8 const* t = &ROM(c);
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memcpy(GSU.pvCache,t,512);
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}
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else
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{
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uint8 const* t1;
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uint8 const* t2;
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uint32 i = 0x10000 - c;
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t1 = &ROM(c);
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t2 = &ROM(0);
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memcpy(GSU.pvCache,t1,i);
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memcpy(&GSU.pvCache[i],t2,512-i);
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}
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}
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#endif
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void FxCacheWriteAccess(uint16 vAddress)
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{
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#if 0
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if(!GSU.bCacheActive)
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{
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uint8 v = GSU.pvCache[GSU.pvCache[vAddress&0x1ff];
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fx_setCache();
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GSU.pvCache[GSU.pvCache[vAddress&0x1ff] = v;
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}
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#endif
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if((vAddress & 0x00f) == 0x00f)
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GSU.vCacheFlags |= 1 << ((vAddress&0x1f0) >> 4);
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}
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void FxFlushCache()
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{
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GSU.vCacheFlags = 0;
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GSU.vCacheBaseReg = 0;
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GSU.bCacheActive = FALSE;
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// GSU.vPipe = 0x1;
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}
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static void fx_backupCache()
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{
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#if 0
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uint32 i;
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uint32 v = GSU.vCacheFlags;
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uint32 c = USEX16(GSU.vCacheBaseReg);
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if(v)
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for(i=0; i<32; i++)
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{
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if(v&1)
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{
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if(c < (0x10000-16))
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{
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uint8 * t = &GSU.pvPrgBank[c];
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memcpy(&GSU.avCacheBackup[i<<4],t,16);
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memcpy(t,&GSU.pvCache[i<<4],16);
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}
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else
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{
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uint8 * t1;
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uint8 * t2;
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uint32 a = 0x10000 - c;
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t1 = &GSU.pvPrgBank[c];
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t2 = &GSU.pvPrgBank[0];
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memcpy(&GSU.avCacheBackup[i<<4],t1,a);
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memcpy(t1,&GSU.pvCache[i<<4],a);
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memcpy(&GSU.avCacheBackup[(i<<4)+a],t2,16-a);
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memcpy(t2,&GSU.pvCache[(i<<4)+a],16-a);
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}
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}
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c = USEX16(c+16);
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v >>= 1;
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}
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#endif
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}
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static void fx_restoreCache()
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{
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#if 0
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uint32 i;
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uint32 v = GSU.vCacheFlags;
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uint32 c = USEX16(GSU.vCacheBaseReg);
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if(v)
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for(i=0; i<32; i++)
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{
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if(v&1)
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{
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if(c < (0x10000-16))
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{
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uint8 * t = &GSU.pvPrgBank[c];
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memcpy(t,&GSU.avCacheBackup[i<<4],16);
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memcpy(&GSU.pvCache[i<<4],t,16);
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}
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else
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{
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uint8 * t1;
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uint8 * t2;
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uint32 a = 0x10000 - c;
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t1 = &GSU.pvPrgBank[c];
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t2 = &GSU.pvPrgBank[0];
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memcpy(t1,&GSU.avCacheBackup[i<<4],a);
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memcpy(&GSU.pvCache[i<<4],t1,a);
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memcpy(t2,&GSU.avCacheBackup[(i<<4)+a],16-a);
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memcpy(&GSU.pvCache[(i<<4)+a],t2,16-a);
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}
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}
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c = USEX16(c+16);
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v >>= 1;
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}
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#endif
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}
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void fx_flushCache()
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{
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fx_restoreCache();
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GSU.vCacheFlags = 0;
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GSU.bCacheActive = FALSE;
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}
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void fx_updateRamBank(uint8 Byte)
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{
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// Update BankReg and Bank pointer
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GSU.vRamBankReg = (uint32)Byte & (FX_RAM_BANKS-1);
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GSU.pvRamBank = GSU.apvRamBank[Byte & 0x3];
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}
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static void fx_readRegisterSpace()
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{
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int i;
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uint8 *p;
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static uint32 avHeight[] = { 128, 160, 192, 256 };
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static uint32 avMult[] = { 16, 32, 32, 64 };
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GSU.vErrorCode = 0;
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/* Update R0-R15 */
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p = GSU.pvRegisters;
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for(i=0; i<16; i++)
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{
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GSU.avReg[i] = *p++;
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GSU.avReg[i] += ((uint32)(*p++)) << 8;
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}
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/* Update other registers */
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p = GSU.pvRegisters;
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GSU.vStatusReg = (uint32)p[GSU_SFR];
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GSU.vStatusReg |= ((uint32)p[GSU_SFR+1]) << 8;
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GSU.vPrgBankReg = (uint32)p[GSU_PBR];
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GSU.vRomBankReg = (uint32)p[GSU_ROMBR];
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GSU.vRamBankReg = ((uint32)p[GSU_RAMBR]) & (FX_RAM_BANKS-1);
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GSU.vCacheBaseReg = (uint32)p[GSU_CBR];
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GSU.vCacheBaseReg |= ((uint32)p[GSU_CBR+1]) << 8;
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/* Update status register variables */
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GSU.vZero = !(GSU.vStatusReg & FLG_Z);
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GSU.vSign = (GSU.vStatusReg & FLG_S) << 12;
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GSU.vOverflow = (GSU.vStatusReg & FLG_OV) << 16;
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GSU.vCarry = (GSU.vStatusReg & FLG_CY) >> 2;
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/* Set bank pointers */
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GSU.pvRamBank = GSU.apvRamBank[GSU.vRamBankReg & 0x3];
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GSU.pvRomBank = GSU.apvRomBank[GSU.vRomBankReg];
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GSU.pvPrgBank = GSU.apvRomBank[GSU.vPrgBankReg];
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/* Set screen pointers */
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GSU.pvScreenBase = &GSU.pvRam[ USEX8(p[GSU_SCBR]) << 10 ];
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i = (int)(!!(p[GSU_SCMR] & 0x04));
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i |= ((int)(!!(p[GSU_SCMR] & 0x20))) << 1;
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GSU.vScreenHeight = GSU.vScreenRealHeight = avHeight[i];
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GSU.vMode = p[GSU_SCMR] & 0x03;
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#if 0
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if(GSU.vMode == 2)
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error illegal color depth GSU.vMode;
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#endif
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if(i == 3)
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GSU.vScreenSize = (256/8) * (256/8) * 32;
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else
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GSU.vScreenSize = (GSU.vScreenHeight/8) * (256/8) * avMult[GSU.vMode];
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if (GSU.vPlotOptionReg & 0x10)
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{
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/* OBJ Mode (for drawing into sprites) */
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GSU.vScreenHeight = 256;
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}
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#if 0
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if(GSU.pvScreenBase + GSU.vScreenSize > GSU.pvRam + (GSU.nRamBanks * 65536))
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error illegal address for screen base register
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#else
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if(GSU.pvScreenBase + GSU.vScreenSize > GSU.pvRam + (GSU.nRamBanks * 65536))
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GSU.pvScreenBase = GSU.pvRam + (GSU.nRamBanks * 65536) - GSU.vScreenSize;
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#endif
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GSU.pfPlot = fx_apfPlotTable[GSU.vMode];
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GSU.pfRpix = fx_apfPlotTable[GSU.vMode + 5];
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fx_ppfOpcodeTable[0x04c] = GSU.pfPlot;
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fx_ppfOpcodeTable[0x14c] = GSU.pfRpix;
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fx_ppfOpcodeTable[0x24c] = GSU.pfPlot;
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fx_ppfOpcodeTable[0x34c] = GSU.pfRpix;
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fx_computeScreenPointers ();
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fx_backupCache();
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}
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void fx_dirtySCBR()
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{
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GSU.vSCBRDirty = TRUE;
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}
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void fx_computeScreenPointers ()
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{
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if (GSU.vMode != GSU.vPrevMode ||
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GSU.vPrevScreenHeight != GSU.vScreenHeight ||
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GSU.vSCBRDirty)
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{
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int i;
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GSU.vSCBRDirty = FALSE;
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|
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/* Make a list of pointers to the start of each screen column */
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switch (GSU.vScreenHeight)
|
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{
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case 128:
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switch (GSU.vMode)
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{
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case 0:
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for (i = 0; i < 32; i++)
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{
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4);
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GSU.x[i] = i << 8;
|
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}
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break;
|
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case 1:
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for (i = 0; i < 32; i++)
|
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{
|
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5);
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GSU.x[i] = i << 9;
|
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}
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break;
|
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case 2:
|
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case 3:
|
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for (i = 0; i < 32; i++)
|
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{
|
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6);
|
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GSU.x[i] = i << 10;
|
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}
|
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break;
|
|
}
|
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break;
|
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case 160:
|
|
switch (GSU.vMode)
|
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{
|
|
case 0:
|
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for (i = 0; i < 32; i++)
|
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{
|
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GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4);
|
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GSU.x[i] = (i << 8) + (i << 6);
|
|
}
|
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break;
|
|
case 1:
|
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for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5);
|
|
GSU.x[i] = (i << 9) + (i << 7);
|
|
}
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6);
|
|
GSU.x[i] = (i << 10) + (i << 8);
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
case 192:
|
|
switch (GSU.vMode)
|
|
{
|
|
case 0:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + (i << 4);
|
|
GSU.x[i] = (i << 8) + (i << 7);
|
|
}
|
|
break;
|
|
case 1:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + (i << 5);
|
|
GSU.x[i] = (i << 9) + (i << 8);
|
|
}
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase + (i << 6);
|
|
GSU.x[i] = (i << 10) + (i << 9);
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
case 256:
|
|
switch (GSU.vMode)
|
|
{
|
|
case 0:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase +
|
|
((i & 0x10) << 9) + ((i & 0xf) << 8);
|
|
GSU.x[i] = ((i & 0x10) << 8) + ((i & 0xf) << 4);
|
|
}
|
|
break;
|
|
case 1:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase +
|
|
((i & 0x10) << 10) + ((i & 0xf) << 9);
|
|
GSU.x[i] = ((i & 0x10) << 9) + ((i & 0xf) << 5);
|
|
}
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
for (i = 0; i < 32; i++)
|
|
{
|
|
GSU.apvScreen[i] = GSU.pvScreenBase +
|
|
((i & 0x10) << 11) + ((i & 0xf) << 10);
|
|
GSU.x[i] = ((i & 0x10) << 10) + ((i & 0xf) << 6);
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
GSU.vPrevMode = GSU.vMode;
|
|
GSU.vPrevScreenHeight = GSU.vScreenHeight;
|
|
}
|
|
}
|
|
|
|
static void fx_writeRegisterSpace()
|
|
{
|
|
int i;
|
|
uint8 *p;
|
|
|
|
p = GSU.pvRegisters;
|
|
for(i=0; i<16; i++)
|
|
{
|
|
*p++ = (uint8)GSU.avReg[i];
|
|
*p++ = (uint8)(GSU.avReg[i] >> 8);
|
|
}
|
|
|
|
/* Update status register */
|
|
if( USEX16(GSU.vZero) == 0 ) SF(Z);
|
|
else CF(Z);
|
|
if( GSU.vSign & 0x8000 ) SF(S);
|
|
else CF(S);
|
|
if(GSU.vOverflow >= 0x8000 || GSU.vOverflow < -0x8000) SF(OV);
|
|
else CF(OV);
|
|
if(GSU.vCarry) SF(CY);
|
|
else CF(CY);
|
|
|
|
p = GSU.pvRegisters;
|
|
p[GSU_SFR] = (uint8)GSU.vStatusReg;
|
|
p[GSU_SFR+1] = (uint8)(GSU.vStatusReg>>8);
|
|
p[GSU_PBR] = (uint8)GSU.vPrgBankReg;
|
|
p[GSU_ROMBR] = (uint8)GSU.vRomBankReg;
|
|
p[GSU_RAMBR] = (uint8)GSU.vRamBankReg;
|
|
p[GSU_CBR] = (uint8)GSU.vCacheBaseReg;
|
|
p[GSU_CBR+1] = (uint8)(GSU.vCacheBaseReg>>8);
|
|
|
|
fx_restoreCache();
|
|
}
|
|
|
|
/* Reset the FxChip */
|
|
void FxReset(struct FxInit_s *psFxInfo)
|
|
{
|
|
int i;
|
|
static uint32 (**appfFunction[])(uint32) = {
|
|
&fx_apfFunctionTable[0],
|
|
#if 0
|
|
&fx_a_apfFunctionTable[0],
|
|
&fx_r_apfFunctionTable[0],
|
|
&fx_ar_apfFunctionTable[0],
|
|
#endif
|
|
};
|
|
static void (**appfPlot[])() = {
|
|
&fx_apfPlotTable[0],
|
|
#if 0
|
|
&fx_a_apfPlotTable[0],
|
|
&fx_r_apfPlotTable[0],
|
|
&fx_ar_apfPlotTable[0],
|
|
#endif
|
|
};
|
|
static void (**appfOpcode[])() = {
|
|
&fx_apfOpcodeTable[0],
|
|
#if 0
|
|
&fx_a_apfOpcodeTable[0],
|
|
&fx_r_apfOpcodeTable[0],
|
|
&fx_ar_apfOpcodeTable[0],
|
|
#endif
|
|
};
|
|
|
|
/* Get function pointers for the current emulation mode */
|
|
fx_ppfFunctionTable = appfFunction[psFxInfo->vFlags & 0x3];
|
|
fx_ppfPlotTable = appfPlot[psFxInfo->vFlags & 0x3];
|
|
fx_ppfOpcodeTable = appfOpcode[psFxInfo->vFlags & 0x3];
|
|
|
|
/* Clear all internal variables */
|
|
memset((uint8*)&GSU,0,sizeof(struct FxRegs_s));
|
|
|
|
/* Set default registers */
|
|
GSU.pvSreg = GSU.pvDreg = &R0;
|
|
|
|
/* Set RAM and ROM pointers */
|
|
GSU.pvRegisters = psFxInfo->pvRegisters;
|
|
GSU.nRamBanks = psFxInfo->nRamBanks;
|
|
GSU.pvRam = psFxInfo->pvRam;
|
|
GSU.nRomBanks = psFxInfo->nRomBanks;
|
|
GSU.pvRom = psFxInfo->pvRom;
|
|
GSU.vPrevScreenHeight = ~0;
|
|
GSU.vPrevMode = ~0;
|
|
|
|
/* The GSU can't access more than 2mb (16mbits) */
|
|
if(GSU.nRomBanks > 0x20)
|
|
GSU.nRomBanks = 0x20;
|
|
|
|
/* Clear FxChip register space */
|
|
memset(GSU.pvRegisters,0,0x300);
|
|
|
|
/* Set FxChip version Number */
|
|
GSU.pvRegisters[0x3b] = 0;
|
|
|
|
/* Make ROM bank table */
|
|
for(i=0; i<256; i++)
|
|
{
|
|
uint32 b = i & 0x7f;
|
|
if (b >= 0x40)
|
|
{
|
|
if (GSU.nRomBanks > 1)
|
|
b %= GSU.nRomBanks;
|
|
else
|
|
b &= 1;
|
|
|
|
GSU.apvRomBank[i] = &GSU.pvRom[ b << 16 ];
|
|
}
|
|
else
|
|
{
|
|
b %= GSU.nRomBanks * 2;
|
|
GSU.apvRomBank[i] = &GSU.pvRom[ (b << 16) + 0x200000];
|
|
}
|
|
}
|
|
|
|
/* Make RAM bank table */
|
|
for(i=0; i<4; i++)
|
|
{
|
|
GSU.apvRamBank[i] = &GSU.pvRam[(i % GSU.nRamBanks) << 16];
|
|
GSU.apvRomBank[0x70 + i] = GSU.apvRamBank[i];
|
|
}
|
|
|
|
/* Start with a nop in the pipe */
|
|
GSU.vPipe = 0x01;
|
|
|
|
/* Set pointer to GSU cache */
|
|
GSU.pvCache = &GSU.pvRegisters[0x100];
|
|
|
|
fx_readRegisterSpace();
|
|
}
|
|
|
|
static uint8 fx_checkStartAddress()
|
|
{
|
|
/* Check if we start inside the cache */
|
|
if(GSU.bCacheActive && R15 >= GSU.vCacheBaseReg && R15 < (GSU.vCacheBaseReg+512))
|
|
return TRUE;
|
|
|
|
/* Check if we're in an unused area */
|
|
#if 0
|
|
if(GSU.vPrgBankReg < 0x40 && R15 < 0x8000)
|
|
return FALSE;
|
|
#endif
|
|
if(GSU.vPrgBankReg >= 0x60 && GSU.vPrgBankReg <= 0x6f)
|
|
return FALSE;
|
|
if(GSU.vPrgBankReg >= 0x74)
|
|
return FALSE;
|
|
|
|
/* Check if we're in RAM and the RAN flag is not set */
|
|
if(GSU.vPrgBankReg >= 0x70 && GSU.vPrgBankReg <= 0x73 && !(SCMR&(1<<3)) )
|
|
return FALSE;
|
|
|
|
/* If not, we're in ROM, so check if the RON flag is set */
|
|
if(!(SCMR&(1<<4)))
|
|
return FALSE;
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
/* Execute until the next stop instruction */
|
|
int FxEmulate(uint32 nInstructions)
|
|
{
|
|
uint32 vCount;
|
|
|
|
/* Read registers and initialize GSU session */
|
|
fx_readRegisterSpace();
|
|
|
|
/* Check if the start address is valid */
|
|
if(!fx_checkStartAddress())
|
|
{
|
|
CF(G);
|
|
fx_writeRegisterSpace();
|
|
#if 0
|
|
GSU.vIllegalAddress = (GSU.vPrgBankReg << 24) | R15;
|
|
return FX_ERROR_ILLEGAL_ADDRESS;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
/* Execute GSU session */
|
|
CF(IRQ);
|
|
|
|
if(GSU.bBreakPoint)
|
|
vCount = fx_ppfFunctionTable[FX_FUNCTION_RUN_TO_BREAKPOINT](nInstructions);
|
|
else
|
|
vCount = fx_ppfFunctionTable[FX_FUNCTION_RUN](nInstructions);
|
|
|
|
/* Store GSU registers */
|
|
fx_writeRegisterSpace();
|
|
|
|
/* Check for error code */
|
|
if(GSU.vErrorCode)
|
|
return GSU.vErrorCode;
|
|
else
|
|
return vCount;
|
|
}
|
|
|
|
/* Breakpoints */
|
|
void FxBreakPointSet(uint32 vAddress)
|
|
{
|
|
GSU.bBreakPoint = TRUE;
|
|
GSU.vBreakPoint = USEX16(vAddress);
|
|
}
|
|
void FxBreakPointClear()
|
|
{
|
|
GSU.bBreakPoint = FALSE;
|
|
}
|
|
|
|
/* Step by step execution */
|
|
int FxStepOver(uint32 nInstructions)
|
|
{
|
|
uint32 vCount;
|
|
fx_readRegisterSpace();
|
|
|
|
/* Check if the start address is valid */
|
|
if(!fx_checkStartAddress())
|
|
{
|
|
CF(G);
|
|
#if 0
|
|
GSU.vIllegalAddress = (GSU.vPrgBankReg << 24) | R15;
|
|
return FX_ERROR_ILLEGAL_ADDRESS;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
if( PIPE >= 0xf0 )
|
|
GSU.vStepPoint = USEX16(R15+3);
|
|
else if( (PIPE >= 0x05 && PIPE <= 0x0f) || (PIPE >= 0xa0 && PIPE <= 0xaf) )
|
|
GSU.vStepPoint = USEX16(R15+2);
|
|
else
|
|
GSU.vStepPoint = USEX16(R15+1);
|
|
vCount = fx_ppfFunctionTable[FX_FUNCTION_STEP_OVER](nInstructions);
|
|
fx_writeRegisterSpace();
|
|
if(GSU.vErrorCode)
|
|
return GSU.vErrorCode;
|
|
else
|
|
return vCount;
|
|
}
|
|
|
|
/* Errors */
|
|
int FxGetErrorCode()
|
|
{
|
|
return GSU.vErrorCode;
|
|
}
|
|
|
|
int FxGetIllegalAddress()
|
|
{
|
|
return GSU.vIllegalAddress;
|
|
}
|
|
|
|
/* Access to internal registers */
|
|
uint32 FxGetColorRegister()
|
|
{
|
|
return GSU.vColorReg & 0xff;
|
|
}
|
|
|
|
uint32 FxGetPlotOptionRegister()
|
|
{
|
|
return GSU.vPlotOptionReg & 0x1f;
|
|
}
|
|
|
|
uint32 FxGetSourceRegisterIndex()
|
|
{
|
|
return GSU.pvSreg - GSU.avReg;
|
|
}
|
|
|
|
uint32 FxGetDestinationRegisterIndex()
|
|
{
|
|
return GSU.pvDreg - GSU.avReg;
|
|
}
|
|
|
|
uint8 FxPipe()
|
|
{
|
|
return GSU.vPipe;
|
|
}
|
|
|