mirror of
https://github.com/dborth/snes9xgx.git
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535 lines
16 KiB
C
535 lines
16 KiB
C
/**********************************************************************************
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Snes9x - Portable Super Nintendo Entertainment System (TM) emulator.
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(c) Copyright 1996 - 2002 Gary Henderson (gary.henderson@ntlworld.com) and
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Jerremy Koot (jkoot@snes9x.com)
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(c) Copyright 2002 - 2004 Matthew Kendora
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(c) Copyright 2002 - 2005 Peter Bortas (peter@bortas.org)
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(c) Copyright 2004 - 2005 Joel Yliluoma (http://iki.fi/bisqwit/)
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(c) Copyright 2001 - 2006 John Weidman (jweidman@slip.net)
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(c) Copyright 2002 - 2006 Brad Jorsch (anomie@users.sourceforge.net),
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funkyass (funkyass@spam.shaw.ca),
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Kris Bleakley (codeviolation@hotmail.com),
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Nach (n-a-c-h@users.sourceforge.net), and
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zones (kasumitokoduck@yahoo.com)
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BS-X C emulator code
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(c) Copyright 2005 - 2006 Dreamer Nom,
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zones
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C4 x86 assembler and some C emulation code
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(c) Copyright 2000 - 2003 _Demo_ (_demo_@zsnes.com),
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Nach,
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zsKnight (zsknight@zsnes.com)
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C4 C++ code
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(c) Copyright 2003 - 2006 Brad Jorsch,
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Nach
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DSP-1 emulator code
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(c) Copyright 1998 - 2006 _Demo_,
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Andreas Naive (andreasnaive@gmail.com)
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Gary Henderson,
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Ivar (ivar@snes9x.com),
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John Weidman,
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Kris Bleakley,
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Matthew Kendora,
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Nach,
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neviksti (neviksti@hotmail.com)
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DSP-2 emulator code
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(c) Copyright 2003 John Weidman,
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Kris Bleakley,
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Lord Nightmare (lord_nightmare@users.sourceforge.net),
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Matthew Kendora,
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neviksti
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DSP-3 emulator code
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(c) Copyright 2003 - 2006 John Weidman,
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Kris Bleakley,
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Lancer,
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z80 gaiden
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DSP-4 emulator code
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(c) Copyright 2004 - 2006 Dreamer Nom,
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John Weidman,
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Kris Bleakley,
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Nach,
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z80 gaiden
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OBC1 emulator code
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(c) Copyright 2001 - 2004 zsKnight,
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pagefault (pagefault@zsnes.com),
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Kris Bleakley,
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Ported from x86 assembler to C by sanmaiwashi
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SPC7110 and RTC C++ emulator code
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(c) Copyright 2002 Matthew Kendora with research by
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zsKnight,
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John Weidman,
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Dark Force
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S-DD1 C emulator code
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(c) Copyright 2003 Brad Jorsch with research by
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Andreas Naive,
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John Weidman
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S-RTC C emulator code
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(c) Copyright 2001-2006 byuu,
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John Weidman
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ST010 C++ emulator code
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(c) Copyright 2003 Feather,
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John Weidman,
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Kris Bleakley,
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Matthew Kendora
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Super FX x86 assembler emulator code
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(c) Copyright 1998 - 2003 _Demo_,
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pagefault,
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zsKnight,
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Super FX C emulator code
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(c) Copyright 1997 - 1999 Ivar,
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Gary Henderson,
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John Weidman
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Sound DSP emulator code is derived from SNEeSe and OpenSPC:
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(c) Copyright 1998 - 2003 Brad Martin
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(c) Copyright 1998 - 2006 Charles Bilyue'
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SH assembler code partly based on x86 assembler code
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(c) Copyright 2002 - 2004 Marcus Comstedt (marcus@mc.pp.se)
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2xSaI filter
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(c) Copyright 1999 - 2001 Derek Liauw Kie Fa
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HQ2x filter
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(c) Copyright 2003 Maxim Stepin (maxim@hiend3d.com)
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Specific ports contains the works of other authors. See headers in
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individual files.
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Snes9x homepage: http://www.snes9x.com
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Permission to use, copy, modify and/or distribute Snes9x in both binary
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and source form, for non-commercial purposes, is hereby granted without
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fee, providing that this license information and copyright notice appear
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with all copies and any derived work.
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This software is provided 'as-is', without any express or implied
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warranty. In no event shall the authors be held liable for any damages
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arising from the use of this software or it's derivatives.
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Snes9x is freeware for PERSONAL USE only. Commercial users should
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seek permission of the copyright holders first. Commercial use includes,
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but is not limited to, charging money for Snes9x or software derived from
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Snes9x, including Snes9x or derivatives in commercial game bundles, and/or
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using Snes9x as a promotion for your commercial product.
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The copyright holders request that bug fixes and improvements to the code
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should be forwarded to them so everyone can benefit from the modifications
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in future versions.
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Super NES and Super Nintendo Entertainment System are trademarks of
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Nintendo Co., Limited and its subsidiary companies.
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**********************************************************************************/
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#ifndef _CPUADDR_H_
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#define _CPUADDR_H_
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typedef enum {
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NONE = 0,
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READ = 1,
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WRITE = 2,
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MODIFY = 3,
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JUMP = 5,
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JSR = 8
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} AccessMode;
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STATIC inline uint8 Immediate8 (AccessMode a) {
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uint8 val = CPU.PCBase[Registers.PCw];
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if(a&READ) OpenBus = val;
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AddCycles(CPU.MemSpeed);
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Registers.PCw++;
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return val;
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}
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STATIC inline uint8 Immediate8Slow (AccessMode a) {
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uint8 val = S9xGetByte(Registers.PBPC);
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if(a&READ) OpenBus = val;
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Registers.PCw++;
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return val;
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}
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STATIC inline uint16 Immediate16 (AccessMode a) {
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uint16 val = READ_WORD(CPU.PCBase+Registers.PCw);
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if(a&READ) OpenBus = (uint8)(val>>8);
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AddCycles(CPU.MemSpeedx2);
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Registers.PCw+=2;
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return val;
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}
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STATIC inline uint16 Immediate16Slow (AccessMode a) {
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uint16 val = S9xGetWord(Registers.PBPC, WRAP_BANK);
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if(a&READ) OpenBus = (uint8)(val>>8);
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Registers.PCw+=2;
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return val;
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}
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STATIC inline uint32 RelativeSlow (AccessMode a) { // branch $xx
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int8 offset = Immediate8Slow(a);
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return ((int16)Registers.PCw + offset) & 0xffff;
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}
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STATIC inline uint32 Relative (AccessMode a) { // branch $xx
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int8 offset = Immediate8(a);
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return ((int16)Registers.PCw + offset) & 0xffff;
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}
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STATIC inline uint32 RelativeLongSlow (AccessMode a) { // BRL $xxxx
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int16 offset = Immediate16Slow(a);
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return ((int32)Registers.PCw + offset) & 0xffff;
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}
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STATIC inline uint32 RelativeLong (AccessMode a) { // BRL $xxxx
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int16 offset = Immediate16(a);
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return ((int32)Registers.PCw + offset) & 0xffff;
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}
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STATIC inline uint32 AbsoluteIndexedIndirectSlow (AccessMode a) { // (a,X)
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uint16 addr;
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if(a&JSR){
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// JSR (a,X) pushes the old address in the middle of loading the new.
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// OpenBus needs to be set to account for this.
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addr = Immediate8Slow(READ);
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if(a==JSR) OpenBus = Registers.PCl;
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addr |= Immediate8Slow(READ)<<8;
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} else {
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addr = Immediate16Slow(READ);
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}
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AddCycles(ONE_CYCLE);
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addr+=Registers.X.W;
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// Address load wraps within the bank
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uint16 addr2 = S9xGetWord(ICPU.ShiftedPB | addr, WRAP_BANK);
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OpenBus = addr2>>8;
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return addr2;
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}
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STATIC inline uint32 AbsoluteIndexedIndirect (AccessMode a) { // (a,X)
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uint16 addr = Immediate16Slow(READ);
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addr+=Registers.X.W;
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// Address load wraps within the bank
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uint16 addr2 = S9xGetWord(ICPU.ShiftedPB | addr, WRAP_BANK);
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OpenBus = addr2>>8;
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return addr2;
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}
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STATIC inline uint32 AbsoluteIndirectLongSlow (AccessMode a) { // [a]
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uint16 addr = Immediate16Slow(READ);
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// No info on wrapping, but it doesn't matter anyway due to mirroring
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uint32 addr2 = S9xGetWord(addr);
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OpenBus=addr2>>8;
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addr2 |= (OpenBus = S9xGetByte(addr+2))<<16;
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return addr2;
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}
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STATIC inline uint32 AbsoluteIndirectLong (AccessMode a) { // [a]
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uint16 addr = Immediate16(READ);
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// No info on wrapping, but it doesn't matter anyway due to mirroring
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uint32 addr2 = S9xGetWord(addr);
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OpenBus=addr2>>8;
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addr2 |= (OpenBus = S9xGetByte(addr+2))<<16;
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return addr2;
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}
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STATIC inline uint32 AbsoluteIndirectSlow (AccessMode a) { // (a)
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// No info on wrapping, but it doesn't matter anyway due to mirroring
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uint16 addr2 = S9xGetWord(Immediate16Slow(READ));
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OpenBus=addr2>>8;
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return addr2;
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}
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STATIC inline uint32 AbsoluteIndirect (AccessMode a) { // (a)
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// No info on wrapping, but it doesn't matter anyway due to mirroring
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uint16 addr2 = S9xGetWord(Immediate16(READ));
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OpenBus=addr2>>8;
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return addr2;
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}
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STATIC inline uint32 AbsoluteSlow (AccessMode a) { // a
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return ICPU.ShiftedDB|Immediate16Slow(a);
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}
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STATIC inline uint32 Absolute (AccessMode a) { // a
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return ICPU.ShiftedDB|Immediate16(a);
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}
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STATIC inline uint32 AbsoluteLongSlow (AccessMode a) { // l
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uint32 addr = Immediate16Slow(READ);
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// JSR l pushes the old bank in the middle of loading the new.
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// OpenBus needs to be set to account for this.
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if(a==JSR) OpenBus = Registers.PB;
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addr |= Immediate8Slow(a)<<16;
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return addr;
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}
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STATIC inline uint32 AbsoluteLong (AccessMode a) { // l
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uint32 addr = READ_3WORD(CPU.PCBase+Registers.PCw);
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AddCycles(CPU.MemSpeedx2+CPU.MemSpeed);
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if(a&READ) OpenBus = addr>>16;
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Registers.PCw+=3;
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return addr;
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}
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STATIC inline uint32 DirectSlow (AccessMode a) { // d
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uint16 addr = Immediate8Slow(a) + Registers.D.W;
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if(Registers.DL!=0) AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 Direct (AccessMode a) { // d
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uint16 addr = Immediate8(a) + Registers.D.W;
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if(Registers.DL!=0) AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 DirectIndirectSlow (AccessMode a) { // (d)
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uint32 addr = S9xGetWord(DirectSlow(READ),
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(!CheckEmulation() || Registers.DL)?WRAP_BANK:WRAP_PAGE);
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if(a&READ) OpenBus=(uint8)(addr>>8);
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addr |= ICPU.ShiftedDB;
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return addr;
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}
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STATIC inline uint32 DirectIndirectE0 (AccessMode a) { // (d)
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uint32 addr = S9xGetWord(Direct(READ));
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if(a&READ) OpenBus = (uint8)(addr>>8);
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addr |= ICPU.ShiftedDB;
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return addr;
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}
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STATIC inline uint32 DirectIndirectE1 (AccessMode a) { // (d)
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uint32 addr = S9xGetWord(DirectSlow(READ),
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Registers.DL?WRAP_BANK:WRAP_PAGE);
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if(a&READ) OpenBus=(uint8)(addr>>8);
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addr |= ICPU.ShiftedDB;
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return addr;
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}
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STATIC inline uint32 DirectIndirectIndexedSlow (AccessMode a) { // (d),Y
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uint32 addr = DirectIndirectSlow(a);
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if(a&WRITE || !CheckIndex() || (addr&0xff)+Registers.YL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 DirectIndirectIndexedE0X0 (AccessMode a) { // (d),Y
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uint32 addr = DirectIndirectE0(a);
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AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 DirectIndirectIndexedE0X1 (AccessMode a) { // (d),Y
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uint32 addr = DirectIndirectE0(a);
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if(a&WRITE || (addr&0xff)+Registers.YL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 DirectIndirectIndexedE1 (AccessMode a) { // (d),Y
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uint32 addr = DirectIndirectE1(a);
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if(a&WRITE || (addr&0xff)+Registers.YL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 DirectIndirectLongSlow (AccessMode a) { // [d]
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uint16 addr = DirectSlow(READ);
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uint32 addr2 = S9xGetWord(addr);
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OpenBus=addr2>>8;
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addr2 |= (OpenBus = S9xGetByte(addr+2))<<16;
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return addr2;
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}
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STATIC inline uint32 DirectIndirectLong (AccessMode a) { // [d]
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uint16 addr = Direct(READ);
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uint32 addr2 = S9xGetWord(addr);
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OpenBus=addr2>>8;
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addr2 |= (OpenBus = S9xGetByte(addr+2))<<16;
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return addr2;
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}
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STATIC inline uint32 DirectIndirectIndexedLongSlow (AccessMode a) { // [d],Y
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return DirectIndirectLongSlow(a) + Registers.Y.W;
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}
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STATIC inline uint32 DirectIndirectIndexedLong (AccessMode a) { // [d],Y
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return DirectIndirectLong(a) + Registers.Y.W;
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}
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STATIC inline uint32 DirectIndexedXSlow (AccessMode a) { // d,X
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pair addr;
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addr.W = DirectSlow(a);
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if(!CheckEmulation() || Registers.DL){
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addr.W+=Registers.X.W;
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} else {
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addr.B.l+=Registers.XL;
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}
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AddCycles(ONE_CYCLE);
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return addr.W;
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}
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STATIC inline uint32 DirectIndexedXE0 (AccessMode a) { // d,X
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uint16 addr = Direct(a) + Registers.X.W;
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AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 DirectIndexedXE1 (AccessMode a) { // d,X
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if(Registers.DL){
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return DirectIndexedXE0(a);
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} else {
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pair addr;
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addr.W = Direct(a);
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addr.B.l+=Registers.XL;
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AddCycles(ONE_CYCLE);
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return addr.W;
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}
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}
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STATIC inline uint32 DirectIndexedYSlow (AccessMode a) { // d,Y
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pair addr;
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addr.W = DirectSlow(a);
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if(!CheckEmulation() || Registers.DL){
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addr.W+=Registers.Y.W;
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} else {
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addr.B.l+=Registers.YL;
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}
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AddCycles(ONE_CYCLE);
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return addr.W;
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}
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STATIC inline uint32 DirectIndexedYE0 (AccessMode a) { // d,Y
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uint16 addr = Direct(a) + Registers.Y.W;
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AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 DirectIndexedYE1 (AccessMode a) { // d,Y
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if(Registers.DL){
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return DirectIndexedYE0(a);
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} else {
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pair addr;
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addr.W = Direct(a);
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addr.B.l+=Registers.YL;
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AddCycles(ONE_CYCLE);
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return addr.W;
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}
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}
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STATIC inline uint32 DirectIndexedIndirectSlow (AccessMode a) { // (d,X)
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uint32 addr = S9xGetWord(DirectIndexedXSlow(READ),
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(!CheckEmulation() || Registers.DL)?WRAP_BANK:WRAP_PAGE);
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if(a&READ) OpenBus=(uint8)(addr>>8);
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return ICPU.ShiftedDB|addr;
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}
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STATIC inline uint32 DirectIndexedIndirectE0 (AccessMode a) { // (d,X)
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uint32 addr = S9xGetWord(DirectIndexedXE0(READ));
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if(a&READ) OpenBus = (uint8)(addr>>8);
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return ICPU.ShiftedDB|addr;
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}
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STATIC inline uint32 DirectIndexedIndirectE1 (AccessMode a) { // (d,X)
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uint32 addr = S9xGetWord(DirectIndexedXE1(READ),
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Registers.DL?WRAP_BANK:WRAP_PAGE);
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if(a&READ) OpenBus=(uint8)(addr>>8);
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return ICPU.ShiftedDB|addr;
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}
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STATIC inline uint32 AbsoluteIndexedXSlow (AccessMode a) { // a,X
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uint32 addr = AbsoluteSlow(a);
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if(a&WRITE || !CheckIndex() || (addr&0xff)+Registers.XL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.X.W);
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}
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STATIC inline uint32 AbsoluteIndexedXX0 (AccessMode a) { // a,X
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uint32 addr = Absolute(a);
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AddCycles(ONE_CYCLE);
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return (addr + Registers.X.W);
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}
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STATIC inline uint32 AbsoluteIndexedXX1 (AccessMode a) { // a,X
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uint32 addr = Absolute(a);
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if(a&WRITE || (addr&0xff)+Registers.XL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.X.W);
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}
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STATIC inline uint32 AbsoluteIndexedYSlow (AccessMode a) { // a,Y
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uint32 addr = AbsoluteSlow(a);
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if(a&WRITE || !CheckIndex() || (addr&0xff)+Registers.YL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 AbsoluteIndexedYX0 (AccessMode a) { // a,Y
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uint32 addr = Absolute(a);
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AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 AbsoluteIndexedYX1 (AccessMode a) { // a,Y
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uint32 addr = Absolute(a);
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if(a&WRITE || (addr&0xff)+Registers.YL>=0x100) AddCycles(ONE_CYCLE);
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return (addr + Registers.Y.W);
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}
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STATIC inline uint32 AbsoluteLongIndexedXSlow (AccessMode a) { // l,X
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return (AbsoluteLongSlow(a) + Registers.X.W);
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}
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STATIC inline uint32 AbsoluteLongIndexedX (AccessMode a) { // l,X
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return (AbsoluteLong(a) + Registers.X.W);
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}
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STATIC inline uint32 StackRelativeSlow (AccessMode a) { // d,S
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uint16 addr = Immediate8Slow(a) + Registers.S.W;
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AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 StackRelative (AccessMode a) { // d,S
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uint16 addr = Immediate8(a) + Registers.S.W;
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AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 StackRelativeIndirectIndexedSlow (AccessMode a) { // (d,S),Y
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uint32 addr=S9xGetWord(StackRelativeSlow(READ));
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if(a&READ) OpenBus = (uint8)(addr>>8);
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addr = (addr+Registers.Y.W+ICPU.ShiftedDB)&0xffffff;
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AddCycles(ONE_CYCLE);
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return addr;
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}
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STATIC inline uint32 StackRelativeIndirectIndexed (AccessMode a) { // (d,S),Y
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uint32 addr=S9xGetWord(StackRelative(READ));
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if(a&READ) OpenBus = (uint8)(addr>>8);
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addr = (addr+Registers.Y.W+ICPU.ShiftedDB)&0xffffff;
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AddCycles(ONE_CYCLE);
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return addr;
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}
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#endif
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