mirror of
https://github.com/Oibaf66/uae-wii.git
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Remove generated files
This commit is contained in:
simon.kagstrom
parent
401d4638e1
commit
d895ea1bea
518
src/blit.h
518
src/blit.h
@ -1,518 +0,0 @@
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STATIC_INLINE uae_u32 blit_func(uae_u32 srca, uae_u32 srcb, uae_u32 srcc, uae_u8 mt)
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{
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switch(mt){
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case 0x0:
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return 0;
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case 0x1:
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return ~(srca | srcb | srcc);
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case 0x2:
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return (srcc & ~(srca | srcb));
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case 0x3:
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return ~(srca | srcb);
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case 0x4:
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return (srcb & ~(srca | srcc));
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case 0x5:
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return ~(srca | srcc);
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case 0x6:
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return (~srca & (srcb ^ srcc));
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case 0x7:
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return ~(srca | (srcb & srcc));
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case 0x8:
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return (~srca & srcb & srcc);
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case 0x9:
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return ~(srca | (srcb ^ srcc));
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case 0xa:
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return (~srca & srcc);
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case 0xb:
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return ~(srca | (srcb & ~srcc));
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case 0xc:
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return (~srca & srcb);
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case 0xd:
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return ~(srca | (~srcb & srcc));
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case 0xe:
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return (~srca & (srcb | srcc));
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case 0xf:
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return ~srca;
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case 0x10:
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return (srca & ~(srcb | srcc));
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case 0x11:
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return ~(srcb | srcc);
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case 0x12:
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return (~srcb & (srca ^ srcc));
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case 0x13:
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return ~(srcb | (srca & srcc));
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case 0x14:
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return (~srcc & (srca ^ srcb));
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case 0x15:
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return ~(srcc | (srca & srcb));
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case 0x16:
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return (srca ^ ((srca & srcb) | (srcb ^ srcc)));
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case 0x17:
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return ~(srca ^ ((srca ^ srcb) & (srca ^ srcc)));
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case 0x18:
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return ((srca ^ srcb) & (srca ^ srcc));
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case 0x19:
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return (srcb ^ (~srcc | (srca & srcb)));
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case 0x1a:
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return (srca ^ (srcc | (srca & srcb)));
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case 0x1b:
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return (srca ^ (srcc | ~(srca ^ srcb)));
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case 0x1c:
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return (srca ^ (srcb | (srca & srcc)));
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case 0x1d:
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return (srca ^ (srcb | ~(srca ^ srcc)));
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case 0x1e:
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return (srca ^ (srcb | srcc));
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case 0x1f:
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return ~(srca & (srcb | srcc));
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case 0x20:
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return (srca & ~srcb & srcc);
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case 0x21:
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return ~(srcb | (srca ^ srcc));
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case 0x22:
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return (~srcb & srcc);
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case 0x23:
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return ~(srcb | (srca & ~srcc));
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case 0x24:
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return ((srca ^ srcb) & (srcb ^ srcc));
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case 0x25:
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return (srca ^ (~srcc | (srca & srcb)));
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case 0x26:
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return (srcb ^ (srcc | (srca & srcb)));
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case 0x27:
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return ~(srca ^ (srcc & (srca ^ srcb)));
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case 0x28:
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return (srcc & (srca ^ srcb));
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case 0x29:
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return ~(srca ^ srcb ^ (srcc | (srca & srcb)));
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case 0x2a:
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return (srcc & ~(srca & srcb));
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case 0x2b:
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return ~(srca ^ ((srca ^ srcb) & (srcb ^ srcc)));
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case 0x2c:
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return (srcb ^ (srca & (srcb | srcc)));
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case 0x2d:
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return (srca ^ (srcb | ~srcc));
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case 0x2e:
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return (srca ^ (srcb | (srca ^ srcc)));
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case 0x2f:
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return ~(srca & (srcb | ~srcc));
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case 0x30:
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return (srca & ~srcb);
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case 0x31:
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return ~(srcb | (~srca & srcc));
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case 0x32:
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return (~srcb & (srca | srcc));
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case 0x33:
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return ~srcb;
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case 0x34:
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return (srcb ^ (srca | (srcb & srcc)));
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case 0x35:
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return (srcb ^ (srca | ~(srcb ^ srcc)));
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case 0x36:
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return (srcb ^ (srca | srcc));
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case 0x37:
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return ~(srcb & (srca | srcc));
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case 0x38:
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return (srca ^ (srcb & (srca | srcc)));
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case 0x39:
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return (srcb ^ (srca | ~srcc));
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case 0x3a:
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return (srcb ^ (srca | (srcb ^ srcc)));
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case 0x3b:
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return ~(srcb & (srca | ~srcc));
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case 0x3c:
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return (srca ^ srcb);
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case 0x3d:
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return (srca ^ (srcb | ~(srca | srcc)));
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case 0x3e:
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return (srca ^ (srcb | (srca ^ (srca | srcc))));
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case 0x3f:
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return ~(srca & srcb);
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case 0x40:
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return (srca & srcb & ~srcc);
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case 0x41:
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return ~(srcc | (srca ^ srcb));
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case 0x42:
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return ((srca ^ srcc) & (srcb ^ srcc));
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case 0x43:
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return (srca ^ (~srcb | (srca & srcc)));
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case 0x44:
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return (srcb & ~srcc);
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case 0x45:
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return ~(srcc | (srca & ~srcb));
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case 0x46:
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return (srcc ^ (srcb | (srca & srcc)));
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case 0x47:
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return ~(srca ^ (srcb & (srca ^ srcc)));
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case 0x48:
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return (srcb & (srca ^ srcc));
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case 0x49:
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return ~(srca ^ srcc ^ (srcb | (srca & srcc)));
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case 0x4a:
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return (srcc ^ (srca & (srcb | srcc)));
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case 0x4b:
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return (srca ^ (~srcb | srcc));
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case 0x4c:
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return (srcb & ~(srca & srcc));
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case 0x4d:
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return (srca ^ ((srca ^ srcb) | ~(srca ^ srcc)));
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case 0x4e:
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return (srca ^ (srcc | (srca ^ srcb)));
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case 0x4f:
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return ~(srca & (~srcb | srcc));
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case 0x50:
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return (srca & ~srcc);
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case 0x51:
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return ~(srcc | (~srca & srcb));
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case 0x52:
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return (srcc ^ (srca | (srcb & srcc)));
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case 0x53:
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return ~(srcb ^ (srca & (srcb ^ srcc)));
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case 0x54:
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return (~srcc & (srca | srcb));
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case 0x55:
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return ~srcc;
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case 0x56:
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return (srcc ^ (srca | srcb));
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case 0x57:
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return ~(srcc & (srca | srcb));
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case 0x58:
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return (srca ^ (srcc & (srca | srcb)));
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case 0x59:
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return (srcc ^ (srca | ~srcb));
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case 0x5a:
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return (srca ^ srcc);
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case 0x5b:
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return (srca ^ (srcc | ~(srca | srcb)));
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case 0x5c:
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return (srcc ^ (srca | (srcb ^ srcc)));
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case 0x5d:
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return ~(srcc & (srca | ~srcb));
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case 0x5e:
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return (srca ^ (srcc | (srca ^ (srca | srcb))));
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case 0x5f:
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return ~(srca & srcc);
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case 0x60:
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return (srca & (srcb ^ srcc));
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case 0x61:
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return ~(srcb ^ srcc ^ (srca | (srcb & srcc)));
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case 0x62:
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return (srcc ^ (srcb & (srca | srcc)));
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case 0x63:
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return (srcb ^ (~srca | srcc));
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case 0x64:
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return (srcb ^ (srcc & (srca | srcb)));
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case 0x65:
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return (srcc ^ (~srca | srcb));
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case 0x66:
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return (srcb ^ srcc);
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case 0x67:
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return (srcb ^ (srcc | ~(srca | srcb)));
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case 0x68:
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return ((srca & srcb) ^ (srcc & (srca | srcb)));
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case 0x69:
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return ~(srca ^ srcb ^ srcc);
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case 0x6a:
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return (srcc ^ (srca & srcb));
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case 0x6b:
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return ~(srca ^ srcb ^ (srcc & (srca | srcb)));
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case 0x6c:
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return (srcb ^ (srca & srcc));
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case 0x6d:
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return ~(srca ^ srcc ^ (srcb & (srca | srcc)));
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case 0x6e:
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return ((~srca & srcb) | (srcb ^ srcc));
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case 0x6f:
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return (~srca | (srcb ^ srcc));
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case 0x70:
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return (srca & ~(srcb & srcc));
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case 0x71:
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return ~(srca ^ ((srca ^ srcb) | (srca ^ srcc)));
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case 0x72:
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return (srcb ^ (srcc | (srca ^ srcb)));
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case 0x73:
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return ~(srcb & (~srca | srcc));
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case 0x74:
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return (srcc ^ (srcb | (srca ^ srcc)));
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case 0x75:
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return ~(srcc & (~srca | srcb));
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case 0x76:
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return (srcb ^ (srcc | (srca ^ (srca & srcb))));
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case 0x77:
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return ~(srcb & srcc);
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case 0x78:
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return (srca ^ (srcb & srcc));
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case 0x79:
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return ~(srcb ^ srcc ^ (srca & (srcb | srcc)));
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case 0x7a:
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return ((srca & ~srcb) | (srca ^ srcc));
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case 0x7b:
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return (~srcb | (srca ^ srcc));
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case 0x7c:
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return ((srca ^ srcb) | (srca & ~srcc));
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case 0x7d:
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return (~srcc | (srca ^ srcb));
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case 0x7e:
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return ((srca ^ srcb) | (srca ^ srcc));
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case 0x7f:
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return ~(srca & srcb & srcc);
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case 0x80:
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return (srca & srcb & srcc);
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case 0x81:
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return ~((srca ^ srcb) | (srca ^ srcc));
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case 0x82:
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return (srcc & ~(srca ^ srcb));
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case 0x83:
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return (srca ^ (~srcb | (srca & ~srcc)));
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case 0x84:
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return (srcb & ~(srca ^ srcc));
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case 0x85:
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return (srca ^ (~srcc | (srca & ~srcb)));
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case 0x86:
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return (srcb ^ srcc ^ (srca & (srcb | srcc)));
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case 0x87:
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return ~(srca ^ (srcb & srcc));
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case 0x88:
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return (srcb & srcc);
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case 0x89:
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return (srcb ^ (~srcc & (~srca | srcb)));
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case 0x8a:
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return (srcc & (~srca | srcb));
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case 0x8b:
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return (srca ^ (~srcb | (srca ^ srcc)));
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case 0x8c:
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return (srcb & (~srca | srcc));
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case 0x8d:
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return (srca ^ (~srcc | (srca ^ srcb)));
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case 0x8e:
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return (srca ^ ((srca ^ srcb) | (srca ^ srcc)));
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case 0x8f:
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return (~srca | (srcb & srcc));
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case 0x90:
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return (srca & ~(srcb ^ srcc));
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case 0x91:
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return (srcb ^ (~srcc | (~srca & srcb)));
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case 0x92:
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return (srca ^ srcc ^ (srcb & (srca | srcc)));
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case 0x93:
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return ~(srcb ^ (srca & srcc));
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case 0x94:
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return (srca ^ srcb ^ (srcc & (srca | srcb)));
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case 0x95:
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return ~(srcc ^ (srca & srcb));
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case 0x96:
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return (srca ^ srcb ^ srcc);
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case 0x97:
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return (srca ^ srcb ^ (srcc | ~(srca | srcb)));
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case 0x98:
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return (srcb ^ (~srcc & (srca | srcb)));
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case 0x99:
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return ~(srcb ^ srcc);
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case 0x9a:
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return (srcc ^ (srca & ~srcb));
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case 0x9b:
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return ~(srcb ^ (srcc & (srca | srcb)));
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case 0x9c:
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return (srcb ^ (srca & ~srcc));
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case 0x9d:
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return ~(srcc ^ (srcb & (srca | srcc)));
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case 0x9e:
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return (srcb ^ srcc ^ (srca | (srcb & srcc)));
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case 0x9f:
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return ~(srca & (srcb ^ srcc));
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case 0xa0:
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return (srca & srcc);
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case 0xa1:
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return (srca ^ (~srcc & (srca | ~srcb)));
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case 0xa2:
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return (srcc & (srca | ~srcb));
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case 0xa3:
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return (srcb ^ (~srca | (srcb ^ srcc)));
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case 0xa4:
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return (srca ^ (~srcc & (srca | srcb)));
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case 0xa5:
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return ~(srca ^ srcc);
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case 0xa6:
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return (srcc ^ (~srca & srcb));
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case 0xa7:
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return ~(srca ^ (srcc & (srca | srcb)));
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case 0xa8:
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return (srcc & (srca | srcb));
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case 0xa9:
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return ~(srcc ^ (srca | srcb));
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case 0xaa:
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return srcc;
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case 0xab:
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return (srcc | ~(srca | srcb));
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case 0xac:
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return (srcb ^ (srca & (srcb ^ srcc)));
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case 0xad:
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return ~(srcc ^ (srca | (srcb & srcc)));
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case 0xae:
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return (srcc | (~srca & srcb));
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case 0xaf:
|
|
||||||
return (~srca | srcc);
|
|
||||||
case 0xb0:
|
|
||||||
return (srca & (~srcb | srcc));
|
|
||||||
case 0xb1:
|
|
||||||
return ~(srca ^ (srcc | (srca ^ srcb)));
|
|
||||||
case 0xb2:
|
|
||||||
return (srca ^ ((srca ^ srcc) & (srcb ^ srcc)));
|
|
||||||
case 0xb3:
|
|
||||||
return (~srcb | (srca & srcc));
|
|
||||||
case 0xb4:
|
|
||||||
return (srca ^ (srcb & ~srcc));
|
|
||||||
case 0xb5:
|
|
||||||
return ~(srcc ^ (srca & (srcb | srcc)));
|
|
||||||
case 0xb6:
|
|
||||||
return (srca ^ srcc ^ (srcb | (srca & srcc)));
|
|
||||||
case 0xb7:
|
|
||||||
return ~(srcb & (srca ^ srcc));
|
|
||||||
case 0xb8:
|
|
||||||
return (srca ^ (srcb & (srca ^ srcc)));
|
|
||||||
case 0xb9:
|
|
||||||
return ~(srcc ^ (srcb | (srca & srcc)));
|
|
||||||
case 0xba:
|
|
||||||
return (srcc | (srca & ~srcb));
|
|
||||||
case 0xbb:
|
|
||||||
return (~srcb | srcc);
|
|
||||||
case 0xbc:
|
|
||||||
return ((srca ^ srcb) | (srca & srcc));
|
|
||||||
case 0xbd:
|
|
||||||
return ((srca ^ srcb) | ~(srca ^ srcc));
|
|
||||||
case 0xbe:
|
|
||||||
return (srcc | (srca ^ srcb));
|
|
||||||
case 0xbf:
|
|
||||||
return (srcc | ~(srca & srcb));
|
|
||||||
case 0xc0:
|
|
||||||
return (srca & srcb);
|
|
||||||
case 0xc1:
|
|
||||||
return (srca ^ (~srcb & (srca | ~srcc)));
|
|
||||||
case 0xc2:
|
|
||||||
return (srca ^ (~srcb & (srca | srcc)));
|
|
||||||
case 0xc3:
|
|
||||||
return ~(srca ^ srcb);
|
|
||||||
case 0xc4:
|
|
||||||
return (srcb & (srca | ~srcc));
|
|
||||||
case 0xc5:
|
|
||||||
return ~(srcb ^ (srca | (srcb ^ srcc)));
|
|
||||||
case 0xc6:
|
|
||||||
return (srcb ^ (~srca & srcc));
|
|
||||||
case 0xc7:
|
|
||||||
return ~(srca ^ (srcb & (srca | srcc)));
|
|
||||||
case 0xc8:
|
|
||||||
return (srcb & (srca | srcc));
|
|
||||||
case 0xc9:
|
|
||||||
return ~(srcb ^ (srca | srcc));
|
|
||||||
case 0xca:
|
|
||||||
return (srcc ^ (srca & (srcb ^ srcc)));
|
|
||||||
case 0xcb:
|
|
||||||
return ~(srcb ^ (srca | (srcb & srcc)));
|
|
||||||
case 0xcc:
|
|
||||||
return srcb;
|
|
||||||
case 0xcd:
|
|
||||||
return (srcb | ~(srca | srcc));
|
|
||||||
case 0xce:
|
|
||||||
return (srcb | (~srca & srcc));
|
|
||||||
case 0xcf:
|
|
||||||
return (~srca | srcb);
|
|
||||||
case 0xd0:
|
|
||||||
return (srca & (srcb | ~srcc));
|
|
||||||
case 0xd1:
|
|
||||||
return ~(srca ^ (srcb | (srca ^ srcc)));
|
|
||||||
case 0xd2:
|
|
||||||
return (srca ^ (~srcb & srcc));
|
|
||||||
case 0xd3:
|
|
||||||
return ~(srcb ^ (srca & (srcb | srcc)));
|
|
||||||
case 0xd4:
|
|
||||||
return (srca ^ ((srca ^ srcb) & (srcb ^ srcc)));
|
|
||||||
case 0xd5:
|
|
||||||
return (~srcc | (srca & srcb));
|
|
||||||
case 0xd6:
|
|
||||||
return (srca ^ srcb ^ (srcc | (srca & srcb)));
|
|
||||||
case 0xd7:
|
|
||||||
return ~(srcc & (srca ^ srcb));
|
|
||||||
case 0xd8:
|
|
||||||
return (srca ^ (srcc & (srca ^ srcb)));
|
|
||||||
case 0xd9:
|
|
||||||
return ~(srcb ^ (srcc | (srca & srcb)));
|
|
||||||
case 0xda:
|
|
||||||
return ((srca & srcb) | (srca ^ srcc));
|
|
||||||
case 0xdb:
|
|
||||||
return ~((srca ^ srcb) & (srcb ^ srcc));
|
|
||||||
case 0xdc:
|
|
||||||
return (srcb | (srca & ~srcc));
|
|
||||||
case 0xdd:
|
|
||||||
return (srcb | ~srcc);
|
|
||||||
case 0xde:
|
|
||||||
return (srcb | (srca ^ srcc));
|
|
||||||
case 0xdf:
|
|
||||||
return (srcb | ~(srca & srcc));
|
|
||||||
case 0xe0:
|
|
||||||
return (srca & (srcb | srcc));
|
|
||||||
case 0xe1:
|
|
||||||
return ~(srca ^ (srcb | srcc));
|
|
||||||
case 0xe2:
|
|
||||||
return (srcc ^ (srcb & (srca ^ srcc)));
|
|
||||||
case 0xe3:
|
|
||||||
return ~(srca ^ (srcb | (srca & srcc)));
|
|
||||||
case 0xe4:
|
|
||||||
return (srcb ^ (srcc & (srca ^ srcb)));
|
|
||||||
case 0xe5:
|
|
||||||
return ~(srca ^ (srcc | (srca & srcb)));
|
|
||||||
case 0xe6:
|
|
||||||
return ((srca & srcb) | (srcb ^ srcc));
|
|
||||||
case 0xe7:
|
|
||||||
return ~((srca ^ srcb) & (srca ^ srcc));
|
|
||||||
case 0xe8:
|
|
||||||
return (srca ^ ((srca ^ srcb) & (srca ^ srcc)));
|
|
||||||
case 0xe9:
|
|
||||||
return (srca ^ srcb ^ (~srcc | (srca & srcb)));
|
|
||||||
case 0xea:
|
|
||||||
return (srcc | (srca & srcb));
|
|
||||||
case 0xeb:
|
|
||||||
return (srcc | ~(srca ^ srcb));
|
|
||||||
case 0xec:
|
|
||||||
return (srcb | (srca & srcc));
|
|
||||||
case 0xed:
|
|
||||||
return (srcb | ~(srca ^ srcc));
|
|
||||||
case 0xee:
|
|
||||||
return (srcb | srcc);
|
|
||||||
case 0xef:
|
|
||||||
return (~srca | srcb | srcc);
|
|
||||||
case 0xf0:
|
|
||||||
return srca;
|
|
||||||
case 0xf1:
|
|
||||||
return (srca | ~(srcb | srcc));
|
|
||||||
case 0xf2:
|
|
||||||
return (srca | (~srcb & srcc));
|
|
||||||
case 0xf3:
|
|
||||||
return (srca | ~srcb);
|
|
||||||
case 0xf4:
|
|
||||||
return (srca | (srcb & ~srcc));
|
|
||||||
case 0xf5:
|
|
||||||
return (srca | ~srcc);
|
|
||||||
case 0xf6:
|
|
||||||
return (srca | (srcb ^ srcc));
|
|
||||||
case 0xf7:
|
|
||||||
return (srca | ~(srcb & srcc));
|
|
||||||
case 0xf8:
|
|
||||||
return (srca | (srcb & srcc));
|
|
||||||
case 0xf9:
|
|
||||||
return (srca | ~(srcb ^ srcc));
|
|
||||||
case 0xfa:
|
|
||||||
return (srca | srcc);
|
|
||||||
case 0xfb:
|
|
||||||
return (srca | ~srcb | srcc);
|
|
||||||
case 0xfc:
|
|
||||||
return (srca | srcb);
|
|
||||||
case 0xfd:
|
|
||||||
return (srca | srcb | ~srcc);
|
|
||||||
case 0xfe:
|
|
||||||
return (srca | srcb | srcc);
|
|
||||||
case 0xff:
|
|
||||||
return 0xFFFFFFFF;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
1519
src/blitfunc.c
1519
src/blitfunc.c
File diff suppressed because it is too large
Load Diff
@ -1,44 +0,0 @@
|
|||||||
extern blitter_func blitdofast_0;
|
|
||||||
extern blitter_func blitdofast_desc_0;
|
|
||||||
extern blitter_func blitdofast_a;
|
|
||||||
extern blitter_func blitdofast_desc_a;
|
|
||||||
extern blitter_func blitdofast_2a;
|
|
||||||
extern blitter_func blitdofast_desc_2a;
|
|
||||||
extern blitter_func blitdofast_30;
|
|
||||||
extern blitter_func blitdofast_desc_30;
|
|
||||||
extern blitter_func blitdofast_3a;
|
|
||||||
extern blitter_func blitdofast_desc_3a;
|
|
||||||
extern blitter_func blitdofast_3c;
|
|
||||||
extern blitter_func blitdofast_desc_3c;
|
|
||||||
extern blitter_func blitdofast_4a;
|
|
||||||
extern blitter_func blitdofast_desc_4a;
|
|
||||||
extern blitter_func blitdofast_6a;
|
|
||||||
extern blitter_func blitdofast_desc_6a;
|
|
||||||
extern blitter_func blitdofast_8a;
|
|
||||||
extern blitter_func blitdofast_desc_8a;
|
|
||||||
extern blitter_func blitdofast_8c;
|
|
||||||
extern blitter_func blitdofast_desc_8c;
|
|
||||||
extern blitter_func blitdofast_9a;
|
|
||||||
extern blitter_func blitdofast_desc_9a;
|
|
||||||
extern blitter_func blitdofast_a8;
|
|
||||||
extern blitter_func blitdofast_desc_a8;
|
|
||||||
extern blitter_func blitdofast_aa;
|
|
||||||
extern blitter_func blitdofast_desc_aa;
|
|
||||||
extern blitter_func blitdofast_b1;
|
|
||||||
extern blitter_func blitdofast_desc_b1;
|
|
||||||
extern blitter_func blitdofast_ca;
|
|
||||||
extern blitter_func blitdofast_desc_ca;
|
|
||||||
extern blitter_func blitdofast_cc;
|
|
||||||
extern blitter_func blitdofast_desc_cc;
|
|
||||||
extern blitter_func blitdofast_d8;
|
|
||||||
extern blitter_func blitdofast_desc_d8;
|
|
||||||
extern blitter_func blitdofast_e2;
|
|
||||||
extern blitter_func blitdofast_desc_e2;
|
|
||||||
extern blitter_func blitdofast_ea;
|
|
||||||
extern blitter_func blitdofast_desc_ea;
|
|
||||||
extern blitter_func blitdofast_f0;
|
|
||||||
extern blitter_func blitdofast_desc_f0;
|
|
||||||
extern blitter_func blitdofast_fa;
|
|
||||||
extern blitter_func blitdofast_desc_fa;
|
|
||||||
extern blitter_func blitdofast_fc;
|
|
||||||
extern blitter_func blitdofast_desc_fc;
|
|
||||||
@ -1,77 +0,0 @@
|
|||||||
#include "sysconfig.h"
|
|
||||||
#include "sysdeps.h"
|
|
||||||
#include "options.h"
|
|
||||||
#include "custom.h"
|
|
||||||
#include "memory.h"
|
|
||||||
#include "blitter.h"
|
|
||||||
#include "blitfunc.h"
|
|
||||||
|
|
||||||
blitter_func * const blitfunc_dofast[256] = {
|
|
||||||
blitdofast_0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_2a, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_30, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_3a, 0, blitdofast_3c, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_4a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_6a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_8a, 0, blitdofast_8c, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_9a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_a8, 0, blitdofast_aa, 0, 0, 0, 0, 0,
|
|
||||||
0, blitdofast_b1, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_ca, 0, blitdofast_cc, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_d8, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_e2, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_ea, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_f0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_fa, 0, blitdofast_fc, 0, 0, 0
|
|
||||||
};
|
|
||||||
|
|
||||||
blitter_func * const blitfunc_dofast_desc[256] = {
|
|
||||||
blitdofast_desc_0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_2a, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_desc_30, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_3a, 0, blitdofast_desc_3c, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_4a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_6a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_8a, 0, blitdofast_desc_8c, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_9a, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_desc_a8, 0, blitdofast_desc_aa, 0, 0, 0, 0, 0,
|
|
||||||
0, blitdofast_desc_b1, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_ca, 0, blitdofast_desc_cc, 0, 0, 0,
|
|
||||||
0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_desc_d8, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_e2, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_ea, 0, 0, 0, 0, 0,
|
|
||||||
blitdofast_desc_f0, 0, 0, 0, 0, 0, 0, 0,
|
|
||||||
0, 0, blitdofast_desc_fa, 0, blitdofast_desc_fc, 0, 0, 0
|
|
||||||
};
|
|
||||||
1767
src/linetoscr.c
1767
src/linetoscr.c
File diff suppressed because it is too large
Load Diff
@ -1,184 +0,0 @@
|
|||||||
#include "sysconfig.h"
|
|
||||||
#include "uae_types.h"
|
|
||||||
#include "readcpu.h"
|
|
||||||
struct instr_def defs68k[] = {
|
|
||||||
{ 60, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }, 16, "ORSR.B #1"},
|
|
||||||
{ 124, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "ORSR.W #1"},
|
|
||||||
{ 192, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 63936, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "CHK2.z #1,s[!Dreg,Areg,Aipi,Apdi,Immd]"},
|
|
||||||
{ 0, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "OR.z #z,d[!Areg]"},
|
|
||||||
{ 572, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }, 16, "ANDSR.B #1"},
|
|
||||||
{ 636, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "ANDSR.W #1"},
|
|
||||||
{ 512, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "AND.z #z,d[!Areg]"},
|
|
||||||
{ 1024, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUB.z #z,d[!Areg]"},
|
|
||||||
{ 1536, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADD.z #z,d[!Areg]"},
|
|
||||||
{ 1728, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "CALLM s[!Dreg,Areg,Aipi,Apdi,Immd]"},
|
|
||||||
{ 1728, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "RTM s[Dreg,Areg]"},
|
|
||||||
{ 2048, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 17, "BTST #1,s[!Areg]"},
|
|
||||||
{ 2112, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BCHG #1,s[!Areg,Immd]"},
|
|
||||||
{ 2176, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BCLR #1,s[!Areg,Immd]"},
|
|
||||||
{ 2240, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BSET #1,s[!Areg,Immd]"},
|
|
||||||
{ 2620, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 } }, 16, "EORSR.B #1"},
|
|
||||||
{ 2684, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "EORSR.W #1"},
|
|
||||||
{ 2560, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "EOR.z #z,d[!Areg]"},
|
|
||||||
{ 3072, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 17, "CMP.z #z,s[!Areg,Immd]"},
|
|
||||||
{ 2752, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "CAS.B #1,s[!Dreg,Areg,Immd,PC8r,PC16]"},
|
|
||||||
{ 3264, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "CAS.W #1,s[!Dreg,Areg,Immd,PC8r,PC16]"},
|
|
||||||
{ 3324, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "CAS2.W #2"},
|
|
||||||
{ 3584, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 65280, 2, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "MOVES.z #1,s[!Dreg,Areg,Immd,PC8r,PC16]"},
|
|
||||||
{ 3776, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "CAS.L #1,s[!Dreg,Areg,Immd,PC8r,PC16]"},
|
|
||||||
{ 3836, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "CAS2.L #2"},
|
|
||||||
{ 256, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MVPMR.W d[Areg-Ad16],Dr"},
|
|
||||||
{ 320, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MVPMR.L d[Areg-Ad16],Dr"},
|
|
||||||
{ 384, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MVPRM.W Dr,d[Areg-Ad16]"},
|
|
||||||
{ 448, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MVPRM.L Dr,d[Areg-Ad16]"},
|
|
||||||
{ 256, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 17, "BTST Dr,s[!Areg]"},
|
|
||||||
{ 320, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BCHG Dr,s[!Areg,Immd]"},
|
|
||||||
{ 384, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BCLR Dr,s[!Areg,Immd]"},
|
|
||||||
{ 448, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 0 }, { 1, 1 }, { 1, 1 } }, 19, "BSET Dr,s[!Areg,Immd]"},
|
|
||||||
{ 4096, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 18, "MOVE.B s,d[!Areg]"},
|
|
||||||
{ 8192, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVEA.L s,d[Areg]"},
|
|
||||||
{ 8192, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 18, "MOVE.L s,d[!Areg]"},
|
|
||||||
{ 12288, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVEA.W s,d[Areg]"},
|
|
||||||
{ 12288, 12, {14,14,14,13,13,13,11,11,11,12,12,12,0,0,0,0}, 61440, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 18, "MOVE.W s,d[!Areg]"},
|
|
||||||
{ 16384, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 0, 0 }, { 1, 4 }, { 0, 0 }, { 1, 4 }, { 1, 0 } }, 48, "NEGX.z d[!Areg]"},
|
|
||||||
{ 16576, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 1, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "MVSR2.W d[!Areg]"},
|
|
||||||
{ 16896, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 2 }, { 1, 3 }, { 1, 2 }, { 1, 2 } }, 32, "CLR.z d[!Areg]"},
|
|
||||||
{ 17088, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 1, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "MVSR2.B d[!Areg]"},
|
|
||||||
{ 17408, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 48, "NEG.z d[!Areg]"},
|
|
||||||
{ 17600, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 16, "MV2SR.B s[!Areg]"},
|
|
||||||
{ 17920, 8, {17,17,13,13,13,14,14,14,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 48, "NOT.z d[!Areg]"},
|
|
||||||
{ 18112, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "MV2SR.W s[!Areg]"},
|
|
||||||
{ 18440, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 2, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 49, "LINK.L Ar,#2"},
|
|
||||||
{ 18432, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 0, 0 }, { 1, 5 }, { 0, 0 }, { 1, 5 }, { 1, 0 } }, 48, "NBCD.B d[!Areg]"},
|
|
||||||
{ 18504, 3, {9,9,9,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "BKPT #k"},
|
|
||||||
{ 18496, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 48, "SWAP.W s[Dreg]"},
|
|
||||||
{ 18496, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "PEA.L s[!Dreg,Areg,Aipi,Apdi,Immd]"},
|
|
||||||
{ 18560, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 48, "EXT.W d[Dreg]"},
|
|
||||||
{ 18560, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "MVMLE.W #1,d[!Dreg,Areg,Aipi]"},
|
|
||||||
{ 18624, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 48, "EXT.L d[Dreg]"},
|
|
||||||
{ 18624, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "MVMLE.L #1,d[!Dreg,Areg,Aipi]"},
|
|
||||||
{ 18880, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 48, "EXT.B d[Dreg]"},
|
|
||||||
{ 18944, 8, {17,17,11,11,11,12,12,12,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 16, "TST.z s"},
|
|
||||||
{ 19136, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 48, "TAS.B d[!Areg]"},
|
|
||||||
{ 19196, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 0, "ILLEGAL"},
|
|
||||||
{ 19456, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "MULL.L #1,s[!Areg]"},
|
|
||||||
{ 19520, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "DIVL.L #1,s[!Areg]"},
|
|
||||||
{ 19584, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 1, "MVMEL.W #1,s[!Dreg,Areg,Apdi,Immd]"},
|
|
||||||
{ 19648, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 1, "MVMEL.L #1,s[!Dreg,Areg,Apdi,Immd]"},
|
|
||||||
{ 20032, 4, {8,8,8,8,0,0,0,0,0,0,0,0,0,0,0,0}, 65520, 0, 0, { { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } }, 16, "TRAP #J"},
|
|
||||||
{ 20048, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 49, "LINK.W Ar,#1"},
|
|
||||||
{ 20056, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 48, "UNLK.L Ar"},
|
|
||||||
{ 20064, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 0, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 16, "MVR2USP.L Ar"},
|
|
||||||
{ 20072, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 0, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 32, "MVUSP2R.L Ar"},
|
|
||||||
{ 20080, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "RESET"},
|
|
||||||
{ 20081, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "NOP"},
|
|
||||||
{ 20082, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 16, "STOP #1"},
|
|
||||||
{ 20083, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 2, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 0, "RTE"},
|
|
||||||
{ 20084, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "RTD #1"},
|
|
||||||
{ 20085, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "RTS"},
|
|
||||||
{ 20086, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } }, 0, "TRAPV"},
|
|
||||||
{ 20087, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 0, "RTR"},
|
|
||||||
{ 20090, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 1, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "MOVEC2 #1"},
|
|
||||||
{ 20091, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 1, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "MOVE2C #1"},
|
|
||||||
{ 20096, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 } }, 128, "JSR.L s[!Dreg,Areg,Aipi,Apdi,Immd]"},
|
|
||||||
{ 16640, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "CHK.L s[!Areg],Dr"},
|
|
||||||
{ 16768, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "CHK.W s[!Areg],Dr"},
|
|
||||||
{ 20160, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 0, 0, { { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 } }, 128, "JMP.L s[!Dreg,Areg,Aipi,Apdi,Immd]"},
|
|
||||||
{ 16832, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "LEA.L s[!Dreg,Areg,Aipi,Apdi,Immd],Ar"},
|
|
||||||
{ 20544, 9, {7,7,7,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "ADDA.W #j,d[Areg]"},
|
|
||||||
{ 20608, 9, {7,7,7,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "ADDA.L #j,d[Areg]"},
|
|
||||||
{ 20480, 11, {7,7,7,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADD.z #j,d[!Areg]"},
|
|
||||||
{ 20800, 9, {7,7,7,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "SUBA.W #j,d[Areg]"},
|
|
||||||
{ 20864, 9, {7,7,7,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "SUBA.L #j,d[Areg]"},
|
|
||||||
{ 20736, 11, {7,7,7,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUB.z #j,d[!Areg]"},
|
|
||||||
{ 20680, 7, {2,2,2,2,15,15,15,0,0,0,0,0,0,0,0,0}, 61688, 0, 0, { { 1, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 } }, 49, "DBcc.W Dr,#1"},
|
|
||||||
{ 20672, 10, {2,2,2,2,13,13,13,14,14,14,0,0,0,0,0,0}, 61632, 0, 0, { { 1, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 } }, 32, "Scc.B d[!Areg]"},
|
|
||||||
{ 20730, 4, {2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "TRAPcc #1"},
|
|
||||||
{ 20731, 4, {2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "TRAPcc #2"},
|
|
||||||
{ 20732, 4, {2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 0, "TRAPcc"},
|
|
||||||
{ 24832, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 } }, 64, "BSR.W #1"},
|
|
||||||
{ 24832, 8, {6,6,6,6,6,6,6,6,0,0,0,0,0,0,0,0}, 65280, 0, 0, { { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 } }, 64, "BSR.B #i"},
|
|
||||||
{ 25087, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 0, 0, { { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 }, { 4, 6 } }, 64, "BSR.L #2"},
|
|
||||||
{ 24576, 4, {3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 0, 0, { { 1, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 } }, 64, "Bcc.W #1"},
|
|
||||||
{ 24576, 12, {3,3,3,3,6,6,6,6,6,6,6,6,0,0,0,0}, 61440, 0, 0, { { 1, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 } }, 64, "Bcc.B #i"},
|
|
||||||
{ 24831, 4, {3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0}, 61695, 0, 0, { { 1, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 }, { 2, 1 } }, 64, "Bcc.L #2"},
|
|
||||||
{ 28672, 11, {15,15,15,5,5,5,5,5,5,5,5,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 18, "MOVE.L #i,Dr"},
|
|
||||||
{ 32768, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "OR.z s[!Areg],Dr"},
|
|
||||||
{ 32960, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "DIVU.W s[!Areg],Dr"},
|
|
||||||
{ 33024, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 0, 0 }, { 1, 4 }, { 0, 0 }, { 1, 4 }, { 1, 0 } }, 19, "SBCD.B d[Dreg],Dr"},
|
|
||||||
{ 33024, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 0, 0 }, { 1, 4 }, { 0, 0 }, { 1, 4 }, { 1, 0 } }, 19, "SBCD.B d[Areg-Apdi],Arp"},
|
|
||||||
{ 33024, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "OR.z Dr,d[!Areg,Dreg]"},
|
|
||||||
{ 33088, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 18, "PACK d[Dreg],Dr"},
|
|
||||||
{ 33088, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 18, "PACK d[Areg-Apdi],Arp"},
|
|
||||||
{ 33152, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 18, "UNPK d[Dreg],Dr"},
|
|
||||||
{ 33152, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 18, "UNPK d[Areg-Apdi],Arp"},
|
|
||||||
{ 33216, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "DIVS.W s[!Areg],Dr"},
|
|
||||||
{ 36864, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUB.z s,Dr"},
|
|
||||||
{ 37056, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "SUBA.W s,Ar"},
|
|
||||||
{ 37120, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 0, 0 }, { 1, 0 }, { 0, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUBX.z d[Dreg],Dr"},
|
|
||||||
{ 37120, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 0, 0 }, { 1, 0 }, { 0, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUBX.z d[Areg-Apdi],Arp"},
|
|
||||||
{ 37120, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "SUB.z Dr,d[!Areg,Dreg]"},
|
|
||||||
{ 37312, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "SUBA.L s,Ar"},
|
|
||||||
{ 45056, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 17, "CMP.z s,Dr"},
|
|
||||||
{ 45248, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 17, "CMPA.W s,Ar"},
|
|
||||||
{ 45504, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 17, "CMPA.L s,Ar"},
|
|
||||||
{ 45312, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 17, "CMPM.z d[Areg-Aipi],ArP"},
|
|
||||||
{ 45312, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "EOR.z Dr,d[!Areg]"},
|
|
||||||
{ 49152, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "AND.z s[!Areg],Dr"},
|
|
||||||
{ 49344, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "MULU.W s[!Areg],Dr"},
|
|
||||||
{ 49408, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 0, 0 }, { 1, 4 }, { 0, 0 }, { 1, 4 }, { 1, 0 } }, 19, "ABCD.B d[Dreg],Dr"},
|
|
||||||
{ 49408, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 0, 0 }, { 1, 4 }, { 0, 0 }, { 1, 4 }, { 1, 0 } }, 19, "ABCD.B d[Areg-Apdi],Arp"},
|
|
||||||
{ 49408, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "AND.z Dr,d[!Areg,Dreg]"},
|
|
||||||
{ 49472, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 51, "EXG.L Dr,d[Dreg]"},
|
|
||||||
{ 49472, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 51, "EXG.L Ar,d[Areg]"},
|
|
||||||
{ 49536, 9, {15,15,15,13,13,13,14,14,14,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 51, "EXG.L Dr,d[Areg]"},
|
|
||||||
{ 49600, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 2 } }, 19, "MULS.W s[!Areg],Dr"},
|
|
||||||
{ 53248, 11, {15,15,15,17,17,11,11,11,12,12,12,0,0,0,0,0}, 61696, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADD.z s,Dr"},
|
|
||||||
{ 53440, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "ADDA.W s,Ar"},
|
|
||||||
{ 53504, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 0, 0 }, { 1, 0 }, { 0, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADDX.z d[Dreg],Dr"},
|
|
||||||
{ 53504, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 0, 0 }, { 1, 0 }, { 0, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADDX.z d[Areg-Apdi],Arp"},
|
|
||||||
{ 53504, 11, {15,15,15,17,17,13,13,13,14,14,14,0,0,0,0,0}, 61696, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ADD.z Dr,d[!Areg,Dreg]"},
|
|
||||||
{ 53696, 9, {15,15,15,11,11,11,12,12,12,0,0,0,0,0,0,0}, 61888, 0, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 19, "ADDA.L s,Ar"},
|
|
||||||
{ 57344, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ASf.z #j,DR"},
|
|
||||||
{ 57352, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "LSf.z #j,DR"},
|
|
||||||
{ 57360, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 0, 0 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "ROXf.z #j,DR"},
|
|
||||||
{ 57368, 9, {7,7,7,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "ROf.z #j,DR"},
|
|
||||||
{ 57376, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 0, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ASf.z Dr,DR"},
|
|
||||||
{ 57384, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 0, 0 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "LSf.z Dr,DR"},
|
|
||||||
{ 57392, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 0, 0 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "ROXf.z Dr,DR"},
|
|
||||||
{ 57400, 9, {15,15,15,4,17,17,16,16,16,0,0,0,0,0,0,0}, 61496, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "ROf.z Dr,DR"},
|
|
||||||
{ 57536, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 0 } }, 19, "ASfW.W d[!Dreg,Areg]"},
|
|
||||||
{ 58048, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, 0, { { 1, 0 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "LSfW.W d[!Dreg,Areg]"},
|
|
||||||
{ 58560, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, 0, { { 0, 0 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "ROXfW.W d[!Dreg,Areg]"},
|
|
||||||
{ 59072, 7, {4,13,13,13,14,14,14,0,0,0,0,0,0,0,0,0}, 65216, 0, 0, { { 1, 1 }, { 1, 0 }, { 1, 0 }, { 1, 2 }, { 1, 0 } }, 19, "ROfW.W d[!Dreg,Areg]"},
|
|
||||||
{ 59584, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "BFTST #1,s[!Areg,Apdi,Aipi,Immd]"},
|
|
||||||
{ 59840, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "BFEXTU #1,s[!Areg,Apdi,Aipi,Immd]"},
|
|
||||||
{ 60096, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFCHG #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"},
|
|
||||||
{ 60352, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "BFEXTS #1,s[!Areg,Apdi,Aipi,Immd]"},
|
|
||||||
{ 60608, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFCLR #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"},
|
|
||||||
{ 60864, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "BFFFO #1,s[!Areg,Apdi,Aipi,Immd]"},
|
|
||||||
{ 61120, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFSET #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"},
|
|
||||||
{ 61376, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 2, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 19, "BFINS #1,s[!Areg,Apdi,Aipi,Immd,PC8r,PC16]"},
|
|
||||||
{ 61952, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FPP #1,s"},
|
|
||||||
{ 62016, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FDBcc #1,s[Areg-Dreg]"},
|
|
||||||
{ 62016, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FScc #1,s[!Areg,Immd,PC8r,PC16]"},
|
|
||||||
{ 62074, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "FTRAPcc #1"},
|
|
||||||
{ 62075, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "FTRAPcc #2"},
|
|
||||||
{ 62076, 0, {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65535, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 0, "FTRAPcc"},
|
|
||||||
{ 62080, 6, {10,10,10,10,10,10,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FBcc #K,#1"},
|
|
||||||
{ 62144, 6, {10,10,10,10,10,10,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "FBcc #K,#2"},
|
|
||||||
{ 62208, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 32, "FSAVE s[!Dreg,Areg,Aipi,Immd,PC8r,PC16]"},
|
|
||||||
{ 62272, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 3, 2, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 16, "FRESTORE s[!Dreg,Areg,Apdi,Immd]"},
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{ 62720, 8, {5,5,5,5,5,12,12,12,0,0,0,0,0,0,0,0}, 65280, 4, 0, { { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 }, { 3, 5 } }, 17, "MMUOP #i,s"},
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{ 62472, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CINVL #p,Ar"},
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{ 62480, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CINVP #p,Ar"},
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{ 62488, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "CINVA #p"},
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{ 62504, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CPUSHL #p,Ar"},
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{ 62512, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 2, "CPUSHP #p,Ar"},
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{ 62520, 5, {18,18,15,15,15,0,0,0,0,0,0,0,0,0,0,0}, 65336, 4, 2, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 0, "CPUSHA #p"},
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{ 63008, 3, {15,15,15,0,0,0,0,0,0,0,0,0,0,0,0,0}, 65528, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 ArP,AxP"},
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{ 62976, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 s[Dreg-Aipi],L"},
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{ 62976, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 L,d[Areg-Aipi]"},
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{ 62976, 6, {11,11,11,12,12,12,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 s[Aind],L"},
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{ 62976, 6, {13,13,13,14,14,14,0,0,0,0,0,0,0,0,0,0}, 65472, 4, 0, { { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 }, { 1, 1 } }, 18, "MOVE16 L,d[Aipi-Aind]"}};
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int n_defs68k = 179;
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Loading…
Reference in New Issue
Block a user