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188 lines
6.0 KiB
C
188 lines
6.0 KiB
C
/* caam_driver.h
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*
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* Copyright (C) 2006-2020 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifndef CAAM_DRIVER_H
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#define CAAM_DRIVER_H
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#define CAAM_BASE 0xf2100000
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#define CAAM_PAGE 0xf0100000
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#define CAAM_PAGE_MAX 6
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/******************************************************************************
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Basic Descriptors
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****************************************************************************/
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/* descriptor commands */
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#define CAAM_KEY 0x00000000
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#define CAAM_LOAD 0x10000000
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#define CAAM_LOAD_CTX 0x10200000
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#define CAAM_IMM 0x00800000
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#define CAAM_FIFO_L 0x20000000
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#define CAAM_FIFO_S 0x60000000
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#define CAAM_FIFO_S_SKEY 0x60260000
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#define CAAM_STORE 0x50000000
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#define CAAM_STORE_CTX 0x50200000
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#define CAAM_MOVE 0x78000000
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#define CAAM_OP 0x80000000
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#define CAAM_SIG 0x90000000
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#define CAAM_JUMP 0xA0000000
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#define CAAM_SEQI 0xF0000000/* SEQ in */
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#define CAAM_SEQO 0xF8000000/* SEQ out */
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#define CAAM_HEAD 0xB0800000
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#define CAAM_NWB 0x00200000
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#define CAAM_BLOB_ENCAP 0x07000000
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#define CAAM_BLOB_DECAP 0x06000000
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#define CAAM_OPID_BLOB 0x000D0000
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/* algorithms modes and types */
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#define CAAM_CLASS1 0x02000000/* i.e. AES */
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#define CAAM_CLASS2 0x04000000/* i.e. hash algos */
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#define CAAM_ENC 0x00000001
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#define CAAM_DEC 0x00000000
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#define CAAM_ALG_INIT 0x00000004
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#define CAAM_ALG_INITF 0x0000000C
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#define CAAM_ALG_UPDATE 0x00000000
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#define CAAM_ALG_FINAL 0x00000008
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/* AES 10h */
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#define CAAM_AESCTR 0x00100000
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#define CAAM_AESCBC 0x00100100
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#define CAAM_AESECB 0x00100200
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#define CAAM_AESCFB 0x00100300
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#define CAAM_AESOFB 0x00100400
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#define CAAM_CMAC 0x00100600
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#define CAAM_AESCCM 0x00100800
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/* HASH 40h */
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#define CAAM_MD5 0x00400000
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#define CAAM_SHA 0x00410000
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#define CAAM_SHA224 0x00420000
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#define CAAM_SHA256 0x00430000
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#define CAAM_SHA384 0x00440000
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#define CAAM_SHA512 0x00450000
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/* HMAC 40h + 10 AAI */
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#define CAAM_HMAC_MD5 0x00400010
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#define CAAM_HMAC_SHA 0x00410010
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#define CAAM_HMAC_SHA224 0x00420010
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#define CAAM_HMAC_SHA256 0x00430010
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#define CAAM_HMAC_SHA384 0x00440010
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#define CAAM_HMAC_SHA512 0x00450010
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#define CAAM_MD5_CTXSZ (16 + 8)
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#define CAAM_SHA_CTXSZ (20 + 8)
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#define CAAM_SHA224_CTXSZ (32 + 8)
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#define CAAM_SHA256_CTXSZ (32 + 8)
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#define CAAM_SHA384_CTXSZ (64 + 8)
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#define CAAM_SHA512_CTXSZ (64 + 8)
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/* RNG 50h */
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#define CAAM_RNG 0x00500000
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/* Used to get raw entropy from TRNG */
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#define CAAM_ENTROPY 0x00500001
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#define FIFOL_TYPE_MSG 0x00100000
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#define FIFOL_TYPE_AAD 0x00300000
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#define FIFOL_TYPE_FC1 0x00010000
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#define FIFOL_TYPE_LC1 0x00020000
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#define FIFOL_TYPE_LC2 0x00040000
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#define FIFOS_TYPE_MSG 0x00300000
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/* continue bit set if more output is expected */
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#define CAAM_FIFOS_CONT 0x00800000
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#define CAAM_PAGE_SZ 4096
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/* RNG Registers */
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#define CAAM_RTMCTL CAAM_BASE + 0X0600
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#define CAAM_RTSDCTL CAAM_BASE + 0X0610
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#define CAAM_RTFRQMIN CAAM_BASE + 0X0618
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#define CAAM_RTFRQMAX CAAM_BASE + 0X061C
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#define CAAM_RDSTA CAAM_BASE + 0X06C0
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#define CAAM_RTSTATUS CAAM_BASE + 0x063C
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/* each of the following 11 RTENT registers are an offset of 4 from RTENT0 */
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#define CAAM_RTENT0 CAAM_BASE + 0x0640
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#define CAAM_RTENT11 CAAM_BASE + 0x066C /* Max RTENT register */
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/* RNG Masks/Values */
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#ifndef CAAM_ENT_DLY
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#define CAAM_ENT_DLY 1200 /* @TODO lower value may gain performance */
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#endif
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#define CAAM_PRGM 0x00010000 /* Set RTMCTL to program state */
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#define CAAM_TRNG 0x00000020 /* Set TRNG access */
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#define CAAM_CTLERR 0x00001000
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#define CAAM_ENTVAL 0x00000400 /* checking RTMCTL for entropy ready */
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/* Input Job Ring Registers */
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#define CAAM_IRBAR0 CAAM_BASE + 0x1004
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#define CAAM_IRSR0 CAAM_BASE + 0x100C
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#define CAAM_IRJAR0 CAAM_BASE + 0x101C
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/* Output Job Ring Registers */
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#define CAAM_ORBAR0 CAAM_BASE + 0x1024
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#define CAAM_ORSR0 CAAM_BASE + 0x102C
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#define CAAM_ORJAR0 CAAM_BASE + 0x103C
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/* Status Registers */
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#define CAAM_STATUS CAAM_BASE + 0x0FD4
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#define CAAM_VERSION_MS CAAM_BASE + 0x0FE8
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#define CAAM_VERSION_LS CAAM_BASE + 0x0FEC
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#define CAMM_SUPPORT_MS CAAM_BASE + 0x0FF0
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#define CAMM_SUPPORT_LS CAAM_BASE + 0x0FF4
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#define CAAM_C1DSR_LS CAAM_BASE + 0x8014
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#define CAAM_C1MR CAAM_BASE + 0x8004
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/* output FIFO is 16 entries deep and each entry has a two 4 byte registers */
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#define CAAM_FIFOO_MS CAAM_BASE + 0x87F0
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#define CAAM_FIFOO_LS CAAM_BASE + 0x87F4
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/* input FIFO is 16 entries deep with each entry having two 4 byte registers
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All data written to it from IP bus should be in big endian format */
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#define CAAM_FIFOI_LS CAAM_BASE + 0x87E0
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/* offset of 4 with range 0 .. 13 */
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#define CAAM_CTX1 CAAM_BASE + 0x8100
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#define CAAM_CTRIV CAAM_CTX1 + 8 /* AES-CTR iv is in 2 and 3 */
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#define CAAM_CBCIV CAAM_CTX1 /* AES-CBC iv is in 1 and 2 */
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/* instantiate RNG and create JDKEK, TDKEK, and TDSK key */
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static unsigned int wc_rng_start[] = {
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CAAM_HEAD | 0x00000006,
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CAAM_OP | CAAM_CLASS1 | CAAM_RNG | 0x00000004, /* Instantiate RNG handle 0 with TRNG */
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CAAM_JUMP | 0x02000001, /* wait for Class1 RNG and jump to next cmd */
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CAAM_LOAD | 0x00880004, /* Load to clear written register */
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0x00000001, /* reset done interrupt */
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CAAM_OP | CAAM_CLASS1 | CAAM_RNG | 0x00001000 /* Generate secure keys */
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};
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#endif /* CAAM_DRIVER_H */
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