mirror of
https://github.com/dborth/vbagx.git
synced 2024-11-22 18:49:18 +01:00
557 lines
14 KiB
C++
557 lines
14 KiB
C++
// -*- C++ -*-
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// VisualBoyAdvance - Nintendo Gameboy/GameboyAdvance (TM) emulator.
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// Copyright (C) 1999-2003 Forgotten
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// Copyright (C) 2004 Forgotten and the VBA development team
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 2, or(at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software Foundation,
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// Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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#ifndef VBA_GBAinline_H
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#define VBA_GBAinline_H
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#include "System.h"
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#include "Port.h"
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#include "RTC.h"
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#include "vmmem.h"
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extern bool cpuSramEnabled;
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extern bool cpuFlashEnabled;
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extern bool cpuEEPROMEnabled;
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extern bool cpuEEPROMSensorEnabled;
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#define VM_USED 1
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#define CPUReadByteQuickDef(addr) \
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map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]
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#define CPUReadHalfWordQuickDef(addr) \
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READ16LE(((u16*)&map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]))
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#define CPUReadMemoryQuickDef(addr) \
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READ32LE(((u32*)&map[(addr)>>24].address[(addr) & map[(addr)>>24].mask]))
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u8 inline CPUReadByteQuick( u32 addr )
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{
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switch(addr >> 24 )
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{
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case 8:
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case 9:
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case 10:
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case 12:
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return VMRead8( addr & 0x1FFFFFF );
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default:
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return CPUReadByteQuickDef(addr);
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}
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return 0;
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}
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u16 inline CPUReadHalfWordQuick( u32 addr )
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{
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switch(addr >> 24)
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{
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case 8:
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case 9:
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case 10:
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case 12:
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return VMRead16( addr & 0x1FFFFFF );
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default:
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return CPUReadHalfWordQuickDef(addr);
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}
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return 0;
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}
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u32 inline CPUReadMemoryQuick( u32 addr )
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{
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switch(addr >> 24)
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{
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case 8:
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case 9:
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case 10:
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case 12:
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return VMRead32( addr & 0x1FFFFFF );
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default:
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return CPUReadMemoryQuickDef(addr);
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}
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return 0;
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}
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inline u32 CPUReadMemory(u32 address)
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{
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#ifdef DEV_VERSION
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if(address & 3)
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{
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if(systemVerbose & VERBOSE_UNALIGNED_MEMORY)
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{
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log("Unaligned word read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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}
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#endif
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u32 value;
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switch(address >> 24)
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{
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case 0:
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if(reg[15].I >> 24)
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{
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if(address < 0x4000)
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{
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_READ)
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{
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log("Illegal word read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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#endif
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value = READ32LE(((u32 *)&biosProtected));
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}
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else goto unreadable;
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}
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else
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value = READ32LE(((u32 *)&bios[address & 0x3FFC]));
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break;
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case 2:
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value = READ32LE(((u32 *)&workRAM[address & 0x3FFFC]));
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break;
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case 3:
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value = READ32LE(((u32 *)&internalRAM[address & 0x7ffC]));
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break;
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case 4:
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if((address < 0x4000400) && ioReadable[address & 0x3fc])
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{
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if(ioReadable[(address & 0x3fc) + 2])
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value = READ32LE(((u32 *)&ioMem[address & 0x3fC]));
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else
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value = READ16LE(((u16 *)&ioMem[address & 0x3fc]));
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}
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else goto unreadable;
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break;
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case 5:
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value = READ32LE(((u32 *)&paletteRAM[address & 0x3fC]));
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break;
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case 6:
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value = READ32LE(((u32 *)&vram[address & 0x1fffc]));
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break;
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case 7:
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value = READ32LE(((u32 *)&oam[address & 0x3FC]));
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break;
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case 8:
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case 9:
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case 10:
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case 11:
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case 12:
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/** Need NGC VM here **/
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//value = READ32LE(((u32 *)&rom[address&0x1FFFFFC]));
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value = VMRead32( address & 0x1FFFFFC );
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break;
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case 13:
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if(cpuEEPROMEnabled)
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// no need to swap this
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return eepromRead(address);
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goto unreadable;
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case 14:
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if(cpuFlashEnabled | cpuSramEnabled)
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// no need to swap this
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return flashRead(address);
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// default
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default:
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unreadable:
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_READ)
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{
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log("Illegal word read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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#endif
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// if(ioMem[0x205] & 0x40) {
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if(armState)
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{
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#if VM_USED
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value = CPUReadMemoryQuick(reg[15].I);
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#else
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value = CPUReadMemoryQuickDef(reg[15].I);
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#endif
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//value = VMRead32(reg[15].I);
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}
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else
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{
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#if VM_USED
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value = CPUReadHalfWordQuick(reg[15].I) |
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CPUReadHalfWordQuick(reg[15].I) << 16;
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#else
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value = CPUReadHalfWordQuickDef(reg[15].I) |
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CPUReadHalfWordQuickDef(reg[15].I) << 16;
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#endif
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//value = VMRead16(reg[15].I) | VMRead16(reg[15].I) << 16;
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}
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// } else {
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// value = *((u32 *)&bios[address & 0x3ffc]);
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// }
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// return 0xFFFFFFFF;
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}
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if(address & 3)
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{
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#ifdef C_CORE
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int shift = (address & 3) << 3;
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value = (value >> shift) | (value << (32 - shift));
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#else
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#ifdef __GNUC__
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asm("and $3, %%ecx;"
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"shl $3 ,%%ecx;"
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"ror %%cl, %0"
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: "=r" (value)
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: "r" (value), "c" (address));
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#else
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__asm {
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mov ecx, address;
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and ecx, 3;
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shl ecx, 3;
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ror [dword ptr value], cl;
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}
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#endif
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#endif
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}
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return value;
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}
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extern u32 myROM[];
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inline u32 CPUReadHalfWord(u32 address)
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{
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#ifdef DEV_VERSION
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if(address & 1)
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{
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if(systemVerbose & VERBOSE_UNALIGNED_MEMORY)
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{
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log("Unaligned halfword read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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}
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#endif
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u32 value;
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switch(address >> 24)
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{
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case 0:
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if (reg[15].I >> 24)
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{
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if(address < 0x4000)
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{
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_READ)
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{
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log("Illegal halfword read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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#endif
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value = READ16LE(((u16 *)&biosProtected[address&2]));
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}
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else goto unreadable;
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}
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else
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value = READ16LE(((u16 *)&bios[address & 0x3FFE]));
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break;
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case 2:
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value = READ16LE(((u16 *)&workRAM[address & 0x3FFFE]));
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break;
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case 3:
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value = READ16LE(((u16 *)&internalRAM[address & 0x7ffe]));
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break;
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case 4:
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if((address < 0x4000400) && ioReadable[address & 0x3fe])
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value = READ16LE(((u16 *)&ioMem[address & 0x3fe]));
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else goto unreadable;
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break;
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case 5:
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value = READ16LE(((u16 *)&paletteRAM[address & 0x3fe]));
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break;
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case 6:
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value = READ16LE(((u16 *)&vram[address & 0x1fffe]));
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break;
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case 7:
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value = READ16LE(((u16 *)&oam[address & 0x3fe]));
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break;
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case 8:
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case 9:
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case 10:
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case 11:
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case 12:
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if(address == 0x80000c4 || address == 0x80000c6 || address == 0x80000c8)
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value = rtcRead(address);
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else
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/** Need NGC VM Here **/
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//value = READ16LE(((u16 *)&rom[address & 0x1FFFFFE]));
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value = VMRead16( address & 0x1FFFFFE );
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break;
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case 13:
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if(cpuEEPROMEnabled)
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// no need to swap this
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return eepromRead(address);
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goto unreadable;
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case 14:
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if(cpuFlashEnabled | cpuSramEnabled)
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// no need to swap this
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return flashRead(address);
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// default
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default:
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unreadable:
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_READ)
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{
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log("Illegal halfword read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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#endif
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extern bool cpuDmaHack;
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extern u32 cpuDmaLast;
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extern int cpuDmaCount;
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if(cpuDmaHack && cpuDmaCount)
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{
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value = (u16)cpuDmaLast;
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}
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else
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{
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if(armState)
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{
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#if VM_USED
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value = CPUReadHalfWordQuick(reg[15].I + (address & 2));
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#else
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value = CPUReadHalfWordQuickDef(reg[15].I + (address & 2));
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#endif
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//value = VMRead16(reg[15].I + (address & 2));
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}
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else
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{
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#if VM_USED
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value = CPUReadHalfWordQuick(reg[15].I);
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#else
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value = CPUReadHalfWordQuickDef(reg[15].I);
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#endif
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//value = VMRead16(reg[15].I);
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}
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}
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// return value;
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// if(address & 1)
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// value = (value >> 8) | ((value & 0xFF) << 24);
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// return 0xFFFF;
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break;
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}
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if(address & 1)
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{
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value = (value >> 8) | (value << 24);
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}
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return value;
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}
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inline u16 CPUReadHalfWordSigned(u32 address)
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{
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u16 value = CPUReadHalfWord(address);
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if((address & 1))
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value = (s8)value;
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return value;
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}
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inline u8 CPUReadByte(u32 address)
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{
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switch(address >> 24)
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{
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case 0:
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if (reg[15].I >> 24)
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{
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if(address < 0x4000)
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{
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_READ)
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{
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log("Illegal byte read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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#endif
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return biosProtected[address & 3];
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}
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else goto unreadable;
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}
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return bios[address & 0x3FFF];
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case 2:
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return workRAM[address & 0x3FFFF];
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case 3:
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return internalRAM[address & 0x7fff];
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case 4:
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if((address < 0x4000400) && ioReadable[address & 0x3ff])
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return ioMem[address & 0x3ff];
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else goto unreadable;
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case 5:
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return paletteRAM[address & 0x3ff];
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case 6:
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return vram[address & 0x1ffff];
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case 7:
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return oam[address & 0x3ff];
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case 8:
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case 9:
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case 10:
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case 11:
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case 12:
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/** Need NGC VM Here **/
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//return rom[address & 0x1FFFFFF];
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return VMRead8( address & 0x1FFFFFF );
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case 13:
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if(cpuEEPROMEnabled)
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return eepromRead(address);
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goto unreadable;
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case 14:
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if(cpuSramEnabled | cpuFlashEnabled)
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return flashRead(address);
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if(cpuEEPROMSensorEnabled)
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{
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switch(address & 0x00008f00)
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{
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case 0x8200:
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return systemGetSensorX() & 255;
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case 0x8300:
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return (systemGetSensorX() >> 8)|0x80;
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case 0x8400:
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return systemGetSensorY() & 255;
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case 0x8500:
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return systemGetSensorY() >> 8;
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}
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}
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// default
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default:
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unreadable:
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_READ)
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{
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log("Illegal byte read: %08x at %08x\n", address, armMode ?
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armNextPC - 4 : armNextPC - 2);
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}
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#endif
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if(armState)
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{
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#if VM_USED
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return CPUReadByteQuick(reg[15].I+(address & 3));
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#else
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return CPUReadByteQuickDef(reg[15].I+(address & 3));
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#endif
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//return VMRead8(reg[15].I+(address & 3));
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}
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else
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{
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#if VM_USED
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return CPUReadByteQuick(reg[15].I+(address & 1));
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#else
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return CPUReadByteQuickDef(reg[15].I+(address & 1));
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#endif
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//return VMRead8(reg[15].I+(address & 1));
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}
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// return 0xFF;
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break;
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}
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}
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inline void CPUWriteMemory(u32 address, u32 value)
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{
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#ifdef DEV_VERSION
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if(address & 3)
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{
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if(systemVerbose & VERBOSE_UNALIGNED_MEMORY)
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{
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log("Unaliagned word write: %08x to %08x from %08x\n",
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value,
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address,
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armMode ? armNextPC - 4 : armNextPC - 2);
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}
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}
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#endif
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switch(address >> 24)
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{
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case 0x02:
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#ifdef SDL
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if(*((u32 *)&freezeWorkRAM[address & 0x3FFFC]))
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cheatsWriteMemory((u32 *)&workRAM[address & 0x3FFFC],
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value,
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*((u32 *)&freezeWorkRAM[address & 0x3FFFC]));
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else
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#endif
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WRITE32LE(((u32 *)&workRAM[address & 0x3FFFC]), value);
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break;
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case 0x03:
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#ifdef SDL
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if(*((u32 *)&freezeInternalRAM[address & 0x7ffc]))
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cheatsWriteMemory((u32 *)&internalRAM[address & 0x7FFC],
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value,
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*((u32 *)&freezeInternalRAM[address & 0x7ffc]));
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else
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#endif
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WRITE32LE(((u32 *)&internalRAM[address & 0x7ffC]), value);
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break;
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case 0x04:
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CPUUpdateRegister((address & 0x3FC), value & 0xFFFF);
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CPUUpdateRegister((address & 0x3FC) + 2, (value >> 16));
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break;
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case 0x05:
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WRITE32LE(((u32 *)&paletteRAM[address & 0x3FC]), value);
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break;
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case 0x06:
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if(address & 0x10000)
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WRITE32LE(((u32 *)&vram[address & 0x17ffc]), value);
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else
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WRITE32LE(((u32 *)&vram[address & 0x1fffc]), value);
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break;
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case 0x07:
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WRITE32LE(((u32 *)&oam[address & 0x3fc]), value);
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break;
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case 0x0D:
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if(cpuEEPROMEnabled)
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{
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eepromWrite(address, value);
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break;
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}
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goto unwritable;
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case 0x0E:
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if(!eepromInUse | cpuSramEnabled | cpuFlashEnabled)
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{
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(*cpuSaveGameFunc)(address, (u8)value);
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break;
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}
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// default
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default:
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unwritable:
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#ifdef DEV_VERSION
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if(systemVerbose & VERBOSE_ILLEGAL_WRITE)
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{
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log("Illegal word write: %08x to %08x from %08x\n",
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value,
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address,
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armMode ? armNextPC - 4 : armNextPC - 2);
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}
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#endif
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break;
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}
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}
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#endif //VBA_GBAinline_H
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