<trclass="memdesc:ga7c3fc6a7f6dc2765f58683e210af4123"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Invalidates a range of cached data, in blocks. <ahref="#ga7c3fc6a7f6dc2765f58683e210af4123">More...</a><br/></td></tr>
<trclass="memdesc:ga3189eaf014ed0ec62c6ecfc5f25d658a"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Flushes a range of cached data, in blocks. <ahref="#ga3189eaf014ed0ec62c6ecfc5f25d658a">More...</a><br/></td></tr>
<trclass="memdesc:ga9fea18f15291b8f6a3e0f57b7459d8ca"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Stores a range of cached data, in blocks. <ahref="#ga9fea18f15291b8f6a3e0f57b7459d8ca">More...</a><br/></td></tr>
<trclass="memdesc:gac08282add83d813b7a5a857da9e62e48"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Similar to <aclass="el"href="group__coreinit__cache.html#ga3189eaf014ed0ec62c6ecfc5f25d658a">DCFlushRange</a>, though this function will <em>not</em> run PowerPC <code>sync</code> and <code>eieio</code> instructions after flushing. <ahref="#gac08282add83d813b7a5a857da9e62e48">More...</a><br/></td></tr>
<trclass="memdesc:gafc3075da855050f179b741e2888adb1e"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Similar to <aclass="el"href="group__coreinit__cache.html#ga9fea18f15291b8f6a3e0f57b7459d8ca">DCStoreRange</a>, though this function will <em>not</em> run PowerPC <code>sync</code> and <code>eieio</code> instructions after storing. <ahref="#gafc3075da855050f179b741e2888adb1e">More...</a><br/></td></tr>
<trclass="memdesc:gaebca39f1de5bbd3b3d46d87894e56b9d"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Zeroes the given area of the data cache (to the nearest block) with a loop of PowerPC <code>dcbz</code> instructions. <ahref="#gaebca39f1de5bbd3b3d46d87894e56b9d">More...</a><br/></td></tr>
<trclass="memdesc:ga5dba3ef0e22806579a099412bced0561"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Gives the processor a hint that the given range of memory is likely to be accessed soon, and that performance would be improved if it were cached. <ahref="#ga5dba3ef0e22806579a099412bced0561">More...</a><br/></td></tr>
<trclass="memdesc:ga4ec28f7c716274c7197a560d09312a08"><tdclass="mdescLeft"> </td><tdclass="mdescRight">Invalidates a range of cached instructions, in blocks. <ahref="#ga4ec28f7c716274c7197a560d09312a08">More...</a><br/></td></tr>
<p>Interface to the low-level caching system of the PowerPC processor. </p>
<p>The cache acts as a middleman between main memory and the processor, speeding up access to frequently-used data. However, the Wii U is not cache-coherent - written data may be cached without updating main memory, and data read from the cache may be out of date with respect to memory. While this isn't a problem for most code, certain hardware accesses may require manual synchronisation of the cache. This is achieved with coreinit's Cache group of functions.</p>
<p>Since the PowerPC has a seperate cache for data and instructions, any data written with the intent of executing it as instructions requires manual flushing and invalidation of the data and instruction caches. </p>
<p>Invalidates a range of cached data, in blocks. </p>
<p>Equivalent to a loop of PowerPC <code>dcbi</code> instructions.</p>
<p>This function forces the next reads from the given address to bypass the the cache and go straight to memory, resulting in slower reads that are guaranteed to reflect main memory.</p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to invalidate.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to invalidate. Will be rounded up to the next 0x20.</td></tr>
</table>
</dd>
</dl>
<dlclass="section note"><dt>Note</dt><dd>Unnecessary use of caching functions can have an adverse performance impact. They should only be used when needed while interfacing with hardware. </dd></dl>
<p>Flushes a range of cached data, in blocks. </p>
<p>Equivalent to a loop of PowerPC <code>dcbf</code> instructions, followed by a <code>sync</code> and <code>eieio</code>.</p>
<p>This function flushes any recently cached data into main memory. This allows other hardware in the console to read the data without worry of main memory being outdated. It will also invalidate cached data.</p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to flush.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to flush. Will be rounded up to the next 0x20.</td></tr>
</table>
</dd>
</dl>
<dlclass="section note"><dt>Note</dt><dd>Unnecessary use of caching functions can have an adverse performance impact. They should only be used when needed while interfacing with hardware. </dd></dl>
<p>Equivalent to a loop of PowerPC <code>dcbst</code> instructions, followed by a <code>sync</code> and <code>eieio</code>.</p>
<p>This function writes any recently cached data into main memory. This allows other hardware in the console to read the data without worry of main memory being outdated. This function does <em>not</em> invalidate the cached data.</p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to store.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to store. Will be rounded up to the next 0x20.</td></tr>
</table>
</dd>
</dl>
<dlclass="section note"><dt>Note</dt><dd>Unnecessary use of caching functions can have an adverse performance impact. They should only be used when needed while interfacing with hardware. </dd></dl>
<p>Similar to <aclass="el"href="group__coreinit__cache.html#ga3189eaf014ed0ec62c6ecfc5f25d658a">DCFlushRange</a>, though this function will <em>not</em> run PowerPC <code>sync</code> and <code>eieio</code> instructions after flushing. </p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to flush.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to flush. Will be rounded up to the next 0x20.</td></tr>
</table>
</dd>
</dl>
<dlclass="section note"><dt>Note</dt><dd>Unnecessary use of caching functions can have an adverse performance impact. They should only be used when needed while interfacing with hardware. </dd></dl>
<p>Similar to <aclass="el"href="group__coreinit__cache.html#ga9fea18f15291b8f6a3e0f57b7459d8ca">DCStoreRange</a>, though this function will <em>not</em> run PowerPC <code>sync</code> and <code>eieio</code> instructions after storing. </p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to store.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to store. Will be rounded up to the next 0x20.</td></tr>
</table>
</dd>
</dl>
<dlclass="section note"><dt>Note</dt><dd>Unnecessary use of caching functions can have an adverse performance impact. They should only be used when needed while interfacing with hardware. </dd></dl>
<p>Zeroes the given area of the data cache (to the nearest block) with a loop of PowerPC <code>dcbz</code> instructions. </p>
<p>This will not affect main memory immediately, though it will eventually trickle down. Can be combined with <aclass="el"href="group__coreinit__cache.html#ga3189eaf014ed0ec62c6ecfc5f25d658a">DCFlushRange</a> or <aclass="el"href="group__coreinit__cache.html#ga9fea18f15291b8f6a3e0f57b7459d8ca">DCStoreRange</a> to efficiently set memory to 0.</p>
<dlclass="section warning"><dt>Warning</dt><dd>The size of the range passed into this function will be internally rounded up to the next multiple of 0x20. Failing to account for this could result in delayed, hard-to-diagnose memory corruption.</dd></dl>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to zero.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to zero. Will be rounded up to the next 0x20. </td></tr>
<p>Gives the processor a hint that the given range of memory is likely to be accessed soon, and that performance would be improved if it were cached. </p>
<p>The processor does not have to cache the requested area, but it may do so in response to this function. This function is equvalent to a loop of PowerPC <code>dcbt</code> instructions.</p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the data to cache.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to cache. Will be rounded up to the next 0x20. </td></tr>
<p>Invalidates a range of cached instructions, in blocks. </p>
<p>Equivalent to a loop of PowerPC <code>icbi</code> instructions.</p>
<p>This function forces the next instruction fetches from the given address to bypass the the cache and go straight to memory, resulting in slower fetches that are guaranteed to reflect main memory.</p>
<dlclass="params"><dt>Parameters</dt><dd>
<tableclass="params">
<tr><tdclass="paramname">addr</td><td>The effective address of the instructions to invalidate.</td></tr>
<tr><tdclass="paramname">size</td><td>The size of the range to invalidate. Will be rounded up to the next 0x20.</td></tr>
</table>
</dd>
</dl>
<dlclass="section note"><dt>Note</dt><dd>Unnecessary use of caching functions can have an adverse performance impact. They should only be used when needed while interfacing with hardware. </dd></dl>
