Exzap
9187044cad
PPCRec: Use named register constants instead of hardcoding regs
2024-10-30 22:40:37 +01:00
Exzap
8219a5f9e7
PPCRec: Fix stack pointer alignment for calls
2024-10-30 03:49:42 +01:00
Exzap
83569ae66b
PPCRec: Avoid relying on undefined behavior in std::copy_backwards
2024-10-30 02:41:43 +01:00
Exzap
a05b6558c4
PPCRec: Handle edge case for x86 shift instructions
2024-10-29 12:38:27 +01:00
Exzap
e33272651c
PPCRec: Optimizations
2024-10-28 23:09:56 +01:00
Exzap
099d1d4e1f
PPCRec: Rework RLWIMI
2024-10-28 09:21:42 +01:00
Exzap
f309d5d8a8
PPCRec: Code cleanup
2024-10-27 14:49:27 +01:00
Exzap
126a682143
PPCRec: Clean up some outdated code
2024-10-26 18:27:10 +02:00
Exzap
636b63fda2
PPCRec: Refactor read/write access tracking for liveness ranges
2024-10-26 12:33:23 +02:00
Exzap
96d7c754f9
PPCRec: Update spill cost calculation
2024-10-25 19:00:11 +02:00
Exzap
70c99fd626
PPCRec: Use 32bit mov for 32bit operations
2024-10-25 09:17:04 +02:00
Exzap
5949e620c5
PPCRec: Reintroduce optimization for BDNZ loops
2024-10-25 08:51:22 +02:00
Exzap
e34a273999
PPCRec: Optimize register allocation
2024-10-23 18:49:15 +02:00
Exzap
f1fa4949d2
Add natvis file for boost::container::small_vector
2024-10-23 08:36:37 +02:00
Exzap
608757dbeb
PPCRec: Fixes and optimizations + rework FRES/FRSQRTE
2024-10-23 08:36:12 +02:00
Exzap
002a03df3d
PPCRec: Implement MCRF, rework DCBZ
2024-10-20 04:25:21 +02:00
Exzap
aa904b6d1c
PPCRec: Clean up code and optimize
2024-10-19 07:28:08 +02:00
Exzap
97ef9524b0
PPCRec: Added dump option for recompiled functions + more fixes
2024-10-19 05:48:38 +02:00
Exzap
8614150116
PPCRec: Support for arbitrary function calls in the IR
...
Used for MFTBU/MFTBL instruction
2024-10-19 02:35:55 +02:00
Exzap
a0ad48c981
PPCRec: Some fixes
2024-10-19 02:11:26 +02:00
Exzap
dcbaa5a43a
PPCRec: Add RA support for instructions with register constraints
...
Also make interval tracking more fine grained and differentiate between input and output edges of each instruction
2024-10-17 12:08:24 +02:00
Exzap
450c0a529c
PPCRec: Simplify RA code and clean it up a bit
2024-09-01 02:53:00 +02:00
Exzap
cc730b4257
PPCRec: Dead code elimination + reintroduce pre-rework optimizations
2024-08-30 01:28:07 +02:00
Exzap
b685a08e60
Fix compile errors due to rebase
2024-08-30 01:28:06 +02:00
Exzap
e5717fb1a8
PPCRec: Implement MFCR and MTCRF
2024-08-30 01:28:06 +02:00
Exzap
b4f2f91d87
PPCRec: FPRs now use the shared register allocator
2024-08-30 01:28:06 +02:00
Exzap
b1c6646831
PPCRec: Further work on support for typed registers in RA
...
Additionally there is no more range limit for virtual RegIDs, making the entire uint16 space available in theory
2024-08-30 01:28:06 +02:00
Exzap
7c767383b4
PPCRec: Partial support for typed registers in RA
2024-08-30 01:28:06 +02:00
Exzap
df74b99761
PPCRec: Initial support for typed registers
2024-08-30 01:28:06 +02:00
Exzap
154aef0c1b
PPCRec: Fix capitalization in include
2024-08-30 01:28:06 +02:00
Exzap
59bd84bc77
PPCRec: Use agnostic breakpoints
2024-08-30 01:28:06 +02:00
Exzap
0577effe41
PPCRec: Use IMLReg type in FPR RA
2024-08-30 01:28:06 +02:00
Exzap
b3676896a9
PPCRec: Unify code + misc RA preparation
...
Whoopsie
2024-08-30 01:28:06 +02:00
Exzap
e86fa57cad
PPCRec: Simplify PPC and IML logic instructions
...
Also implement PPC NAND instruction
2024-08-30 01:28:06 +02:00
Exzap
3ba9460dc1
PPCRec: Use IMLReg in more places, unify and simplify var names
2024-08-30 01:28:06 +02:00
Exzap
b4f2e02e55
PPCRec: Refactor load/store instructions
2024-08-30 01:28:06 +02:00
Exzap
a1c8f6fd37
PPCRec: Refactoring and clean up
2024-08-30 01:28:06 +02:00
Exzap
c4b9fff24a
PPCRec: Rework CR bit handling
...
CR bits are now resident in registers instead of being baked into the instruction definitions. Same for XER SO, and LWARX reservation EA and value.
Reworked LWARX/STWCX, CRxx ops, compare and branch instructions. As well as RC bit handling. Not all CR-related instructions are reimplemented yet.
Introduced atomic_cmp_store operation to allow implementing STWCX in architecture agnostic IML
Removed legacy CR-based compare and jump operations
2024-08-30 01:28:06 +02:00
Exzap
ff09940d03
PPCRec: Avoid complex optimizations in backend
...
It's better to do it in a lowering pass so that the backend code can be kept as simple as possible
2024-08-30 01:28:06 +02:00
Exzap
37256ac589
PPCRec: Rework carry bit and generalize carry IML instructions
...
Carry bit is now resident in a register-allocated GPR instead of being backed directly into IML instructions
All the PowerPC carry ADD* and SUB* instructions as well as SRAW/SRAWI have been reworked to use more generalized IML instructions for handling carry
IML instructions now support two named output registers instead of only one (easily extendable to arbitrary count)
2024-08-30 01:28:06 +02:00
Exzap
8df0281baa
PPCRec: Further unify CR code
2024-08-30 01:28:06 +02:00
Exzap
2535cf43d8
PPCRec: Streamline instructions + unify code for CR updates
2024-08-30 01:28:05 +02:00
Exzap
91f972753e
PPCRec: New compare and cond jump instrs, update RA
...
Storing the condition result in a register instead of imitating PPC CR lets us simplify the backend a lot. Only implemented as PoC for BDZ/BDNZ so far.
2024-08-30 01:28:05 +02:00
Exzap
ac22a38d68
PPCRec: New x86-64 code emitter
2024-08-30 01:28:05 +02:00
Exzap
53139cd8b2
PPCRec: Rename register constants to avoid name collision
2024-08-30 01:28:05 +02:00
Exzap
832b761c5e
PPCRec: Make register pool for RA configurable
2024-08-30 01:28:05 +02:00
Exzap
d308252177
PPCRec: Make LSWI/STWSI more generic + GPR temporaries storage
2024-08-30 01:28:05 +02:00
Exzap
9dc820795f
PPCRec: Clean up unused flags
2024-08-30 01:28:05 +02:00
Exzap
93f56159a1
PPCRec: Remove now unused PPC_ENTER and jumpMarkAddress
2024-08-30 01:28:05 +02:00
Exzap
874e376361
PPCRec: Fix single segment loop not being detected
...
Also removed associatedPPCAddress field from IMLInstruction as it's no longer used
2024-08-30 01:28:05 +02:00
