691 Commits

Author SHA1 Message Date
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dcbaa5a43a PPCRec: Add RA support for instructions with register constraints
Also make interval tracking more fine grained and differentiate between input and output edges of each instruction
2024-10-17 12:08:24 +02:00
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450c0a529c PPCRec: Simplify RA code and clean it up a bit 2024-09-01 02:53:00 +02:00
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cc730b4257 PPCRec: Dead code elimination + reintroduce pre-rework optimizations 2024-08-30 01:28:07 +02:00
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b685a08e60 Fix compile errors due to rebase 2024-08-30 01:28:06 +02:00
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e5717fb1a8 PPCRec: Implement MFCR and MTCRF 2024-08-30 01:28:06 +02:00
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b4f2f91d87 PPCRec: FPRs now use the shared register allocator 2024-08-30 01:28:06 +02:00
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b1c6646831 PPCRec: Further work on support for typed registers in RA
Additionally there is no more range limit for virtual RegIDs, making the entire uint16 space available in theory
2024-08-30 01:28:06 +02:00
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7c767383b4 PPCRec: Partial support for typed registers in RA 2024-08-30 01:28:06 +02:00
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df74b99761 PPCRec: Initial support for typed registers 2024-08-30 01:28:06 +02:00
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154aef0c1b PPCRec: Fix capitalization in include 2024-08-30 01:28:06 +02:00
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59bd84bc77 PPCRec: Use agnostic breakpoints 2024-08-30 01:28:06 +02:00
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0577effe41 PPCRec: Use IMLReg type in FPR RA 2024-08-30 01:28:06 +02:00
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b3676896a9 PPCRec: Unify code + misc RA preparation
Whoopsie
2024-08-30 01:28:06 +02:00
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e86fa57cad PPCRec: Simplify PPC and IML logic instructions
Also implement PPC NAND instruction
2024-08-30 01:28:06 +02:00
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3ba9460dc1 PPCRec: Use IMLReg in more places, unify and simplify var names 2024-08-30 01:28:06 +02:00
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b4f2e02e55 PPCRec: Refactor load/store instructions 2024-08-30 01:28:06 +02:00
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a1c8f6fd37 PPCRec: Refactoring and clean up 2024-08-30 01:28:06 +02:00
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c4b9fff24a PPCRec: Rework CR bit handling
CR bits are now resident in registers instead of being baked into the instruction definitions. Same for XER SO, and LWARX reservation EA and value.

Reworked LWARX/STWCX, CRxx ops, compare and branch instructions. As well as RC bit handling. Not all CR-related instructions are reimplemented yet.

Introduced atomic_cmp_store operation to allow implementing STWCX in architecture agnostic IML

Removed legacy CR-based compare and jump operations
2024-08-30 01:28:06 +02:00
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ff09940d03 PPCRec: Avoid complex optimizations in backend
It's better to do it in a lowering pass so that the backend code can be kept as simple as possible
2024-08-30 01:28:06 +02:00
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37256ac589 PPCRec: Rework carry bit and generalize carry IML instructions
Carry bit is now resident in a register-allocated GPR instead of being backed directly into IML instructions

All the PowerPC carry ADD* and SUB* instructions as well as SRAW/SRAWI have been reworked to use more generalized IML instructions for handling carry

IML instructions now support two named output registers instead of only one (easily extendable to arbitrary count)
2024-08-30 01:28:06 +02:00
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8df0281baa PPCRec: Further unify CR code 2024-08-30 01:28:06 +02:00
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2535cf43d8 PPCRec: Streamline instructions + unify code for CR updates 2024-08-30 01:28:05 +02:00
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91f972753e PPCRec: New compare and cond jump instrs, update RA
Storing the condition result in a register instead of imitating PPC CR lets us simplify the backend a lot. Only implemented as PoC for BDZ/BDNZ so far.
2024-08-30 01:28:05 +02:00
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ac22a38d68 PPCRec: New x86-64 code emitter 2024-08-30 01:28:05 +02:00
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53139cd8b2 PPCRec: Rename register constants to avoid name collision 2024-08-30 01:28:05 +02:00
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832b761c5e PPCRec: Make register pool for RA configurable 2024-08-30 01:28:05 +02:00
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d308252177 PPCRec: Make LSWI/STWSI more generic + GPR temporaries storage 2024-08-30 01:28:05 +02:00
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9dc820795f PPCRec: Clean up unused flags 2024-08-30 01:28:05 +02:00
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93f56159a1 PPCRec: Remove now unused PPC_ENTER and jumpMarkAddress 2024-08-30 01:28:05 +02:00
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874e376361 PPCRec: Fix single segment loop not being detected
Also removed associatedPPCAddress field from IMLInstruction as it's no longer used
2024-08-30 01:28:05 +02:00
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8d972d2500 PPCRec: Unify BCCTR and BCLR code
Instead of having fixed macros for BCCTR/BCCTRL/BCLR/BCLRL we now have only one single macro instruction that takes the jump destination as a register parameter.
This also allows us to reuse an already loaded LR register (by something like MTLR) instead of loading it again from memory.

As a necessary requirement for this: The register allocator now has support for read operations in suffix instructions
2024-08-30 01:28:05 +02:00
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a5f6faac8a PPCRec: Fix merge conflicts 2024-08-30 01:28:05 +02:00
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ce8dc5526c PPCRec: Reworked IML builder to work with basic-blocks
Intermediate commit while I'm still fixing things but I didn't want to pile on too many changes in a single commit.
New:
Reworked PPC->IML converter to first create a graph of basic blocks and then turn those into IML segment(s). This was mainly done to decouple IML design from having PPC specific knowledge like branch target addresses. The previous design also didn't allow to preserve cycle counting properly in all cases since it was based on IML instruction counting.
The new solution supports functions with non-continuous body. A pretty common example for this is when functions end with a trailing B instruction to some other place.

Current limitations:
- BL inlining not implemented
- MFTB not implemented
- BCCTR and BCLR are only partially implemented

Undo vcpkg change
2024-08-30 01:28:05 +02:00
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db60ea6535 PPCRec: Move X64 files into subdirectory and rename 2024-08-30 00:47:55 +02:00
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27f70d5f34 PPCRec: Emit x86 movd for non-AVX + more restructuring 2024-08-30 00:47:54 +02:00
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d1fe1a905f PPCRec: Move IML register allocator 2024-08-30 00:47:54 +02:00
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e53c6ad2e9 PPCRec: Move IML optimizer file 2024-08-30 00:47:54 +02:00
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101a2ef911 PPCRec: Move analyzer file + move some funcs to IMLInstruction 2024-08-30 00:47:54 +02:00
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625874a753 PPCRec: Move debug printing + smaller clean up 2024-08-30 00:47:54 +02:00
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5b2bc7e03a PPCRec: Rename IML structs for better clarity 2024-08-30 00:47:54 +02:00
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b1b46f3d1f PPCRec: Move Segment and Instruction struct into separate files 2024-08-30 00:47:54 +02:00
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0265108e56 PPCRec: Use vector for instruction list 2024-08-30 00:47:54 +02:00
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f523b2152d PPCRec: Use vector for segment list + deduplicate RA file 2024-08-30 00:47:54 +02:00
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4c16397cf4 Latte: Fix race condition on close during game boot 2024-08-30 00:47:54 +02:00
squidbus
9a53b19403
CI+build: Improve macOS builds (#1310) 2024-08-28 11:06:49 +02:00
Cemu-Language CI
03484d2146 Update translation files 2024-08-28 09:05:50 +00:00
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1234e2c118
Preparations for 2.1 (#1306) v2.1 2024-08-26 11:43:38 +02:00
Cemu-Language CI
d7f39aab05 Update translation files 2024-08-26 09:16:11 +00:00
bl
dc9d99b03b
nn_fp: Implement GetMyComment and UpdateCommentAsync (#1173) 2024-08-24 21:03:03 +02:00
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573c98b2f8 GfxPack: Workaround for invisible detail panel
Fixes #1307
There is probably a better way to calculate the maximum width. But this suffices for now as a workaround
v2.0-95
2024-08-23 19:26:33 +02:00