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27 lines
1.3 KiB
Plaintext
27 lines
1.3 KiB
Plaintext
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Here's the format of the YM2612 test register ($21), as best as I can
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tell:
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bit 7 - If bit 6 set, select 0=LSB, 1=MSB of serial data
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bit 6 - If set, reading status returns serial data LSB or MSB instead of
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status flags
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bit 5 - If set, only the attack phase and possibly decay occur, there is
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no sustain o release. It sounds like each channel was keyed-on rapidly.
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When the bit is cleared, the channels resume their original position
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within the envelope so this bit doesn't have any lasting change on
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them.
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bit 4 - Data sent to DAC is inverted - this is *really* loud, so turn
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down the volume before using this bit. ;)
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bit 3 - Audio output is muted, (the PSG still works of course) bits 4,5
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will make sound faintly audible when set in conjunction.
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bit 2 - Timer A and B run 24 times faster.
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bits 1,0 - No effect.
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Bits 7, 6 allow you to read the serial data sent from the YM2612 to the
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DAC. (the other chip, YM3012 - not the DAC at $2A/$2B) I'm unsure of the
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exact format, it's probably similar to the YM2151. Bit 4 inverts the
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data sent to the DAC, but not the data read from the status register.
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Compared to the YM2151 test register documented in MAME, the last 3 bits
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may have something to do with the LFO. And I'm also not entirely sure
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about the MSB/LSB order for bit 6. Other than that the two work in a
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mostly identical way.
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