2017-09-23 13:26:26 +02:00
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/*
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* Copyright (C) 2017 Alexey Khokholov (Nuke.YKT)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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*
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* - Redistributions may not be sold, nor may they be used in a commercial
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* product or activity.
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*
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* - Redistributions that are modified from the original source must include the
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* complete source code, including the source code for all components used by a
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* binary built from the modified sources. However, as a special exception, the
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* source code distributed need not include anything that is normally distributed
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* (in either source or binary form) with the major components (compiler, kernel,
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* and so on) of the operating system on which the executable runs, unless that
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* component itself accompanies the executable.
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*
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* - Redistributions must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* Nuked OPN2(Yamaha YM3438) emulator.
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* Thanks:
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* Silicon Pr0n:
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* Yamaha YM3438 decap and die shot(digshadow).
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* OPLx decapsulated(Matthew Gambrell, Olli Niemitalo):
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* OPL2 ROMs.
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*
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2017-10-05 17:25:16 +02:00
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* version: 1.0.7
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2017-09-23 13:26:26 +02:00
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*/
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2017-09-23 05:52:45 +02:00
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#ifndef YM3438_H
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#define YM3438_H
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2017-09-28 18:45:49 +02:00
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enum {
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ym3438_type_discrete = 0, /* Discrete YM3438 (Teradrive) */
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ym3438_type_asic = 1, /* ASIC YM3438 (MD1 VA7, MD2, MD3, etc) */
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ym3438_type_ym2612 = 2 /* YM2612 (MD1, MD2 VA2) */
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};
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2017-09-26 04:18:19 +02:00
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#include <stdint.h>
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2017-09-23 05:52:45 +02:00
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typedef uintptr_t Bitu;
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typedef intptr_t Bits;
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typedef uint64_t Bit64u;
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typedef int64_t Bit64s;
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typedef uint32_t Bit32u;
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typedef int32_t Bit32s;
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typedef uint16_t Bit16u;
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typedef int16_t Bit16s;
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typedef uint8_t Bit8u;
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typedef int8_t Bit8s;
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typedef struct
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{
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2017-09-28 18:45:49 +02:00
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Bit32u cycles;
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Bit32u slot;
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Bit32u channel;
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Bit16s mol, mor;
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/* IO */
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Bit16u write_data;
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Bit8u write_a;
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Bit8u write_d;
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Bit8u write_a_en;
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Bit8u write_d_en;
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Bit8u write_busy;
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Bit8u write_busy_cnt;
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Bit8u write_fm_address;
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Bit8u write_fm_data;
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Bit8u write_fm_mode_a;
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Bit16u address;
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Bit8u data;
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Bit8u pin_test_in;
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Bit8u pin_irq;
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Bit8u busy;
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/* LFO */
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Bit8u lfo_en;
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Bit8u lfo_freq;
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Bit8u lfo_pm;
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Bit8u lfo_am;
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Bit8u lfo_cnt;
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Bit8u lfo_inc;
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Bit8u lfo_quotient;
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/* Phase generator */
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Bit16u pg_fnum;
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Bit8u pg_block;
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Bit8u pg_kcode;
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Bit32u pg_inc[24];
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Bit32u pg_phase[24];
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Bit8u pg_reset[24];
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Bit32u pg_read;
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/* Envelope generator */
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Bit8u eg_cycle;
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Bit8u eg_cycle_stop;
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Bit8u eg_shift;
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Bit8u eg_shift_lock;
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Bit8u eg_timer_low_lock;
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Bit16u eg_timer;
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Bit8u eg_timer_inc;
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Bit16u eg_quotient;
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Bit8u eg_custom_timer;
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Bit8u eg_rate;
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Bit8u eg_ksv;
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Bit8u eg_inc;
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Bit8u eg_ratemax;
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Bit8u eg_sl[2];
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Bit8u eg_lfo_am;
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Bit8u eg_tl[2];
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Bit8u eg_state[24];
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Bit16u eg_level[24];
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Bit16u eg_out[24];
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Bit8u eg_kon[24];
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Bit8u eg_kon_csm[24];
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Bit8u eg_kon_latch[24];
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Bit8u eg_csm_mode[24];
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Bit8u eg_ssg_enable[24];
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Bit8u eg_ssg_pgrst_latch[24];
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Bit8u eg_ssg_repeat_latch[24];
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Bit8u eg_ssg_hold_up_latch[24];
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Bit8u eg_ssg_dir[24];
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Bit8u eg_ssg_inv[24];
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Bit32u eg_read[2];
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Bit8u eg_read_inc;
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/* FM */
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Bit16s fm_op1[6][2];
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Bit16s fm_op2[6];
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Bit16s fm_out[24];
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Bit16u fm_mod[24];
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/* Channel */
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Bit16s ch_acc[6];
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Bit16s ch_out[6];
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Bit16s ch_lock;
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Bit8u ch_lock_l;
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Bit8u ch_lock_r;
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Bit16s ch_read;
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/* Timer */
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Bit16u timer_a_cnt;
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Bit16u timer_a_reg;
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Bit8u timer_a_load_lock;
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Bit8u timer_a_load;
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Bit8u timer_a_enable;
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Bit8u timer_a_reset;
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Bit8u timer_a_load_latch;
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Bit8u timer_a_overflow_flag;
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Bit8u timer_a_overflow;
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Bit16u timer_b_cnt;
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Bit8u timer_b_subcnt;
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Bit16u timer_b_reg;
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Bit8u timer_b_load_lock;
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Bit8u timer_b_load;
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Bit8u timer_b_enable;
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Bit8u timer_b_reset;
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Bit8u timer_b_load_latch;
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Bit8u timer_b_overflow_flag;
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Bit8u timer_b_overflow;
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/* Register set */
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Bit8u mode_test_21[8];
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Bit8u mode_test_2c[8];
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Bit8u mode_ch3;
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Bit8u mode_kon_channel;
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Bit8u mode_kon_operator[4];
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Bit8u mode_kon[24];
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Bit8u mode_csm;
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Bit8u mode_kon_csm;
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Bit8u dacen;
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Bit16s dacdata;
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Bit8u ks[24];
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Bit8u ar[24];
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Bit8u sr[24];
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Bit8u dt[24];
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Bit8u multi[24];
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Bit8u sl[24];
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Bit8u rr[24];
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Bit8u dr[24];
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Bit8u am[24];
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Bit8u tl[24];
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Bit8u ssg_eg[24];
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Bit16u fnum[6];
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Bit8u block[6];
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Bit8u kcode[6];
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Bit16u fnum_3ch[6];
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Bit8u block_3ch[6];
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Bit8u kcode_3ch[6];
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Bit8u reg_a4;
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Bit8u reg_ac;
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Bit8u connect[6];
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Bit8u fb[6];
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Bit8u pan_l[6], pan_r[6];
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Bit8u ams[6];
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Bit8u pms[6];
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2017-09-23 05:52:45 +02:00
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} ym3438_t;
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2017-09-29 11:01:03 +02:00
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void OPN2_Reset(ym3438_t *chip);
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void OPN2_SetChipType(Bit32u type);
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2017-09-23 05:52:45 +02:00
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void OPN2_Clock(ym3438_t *chip, Bit32u *buffer);
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void OPN2_Write(ym3438_t *chip, Bit32u port, Bit8u data);
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void OPN2_SetTestPin(ym3438_t *chip, Bit32u value);
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Bit32u OPN2_ReadTestPin(ym3438_t *chip);
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Bit32u OPN2_ReadIRQPin(ym3438_t *chip);
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Bit8u OPN2_Read(ym3438_t *chip, Bit32u port);
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#endif
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