2011-07-14 00:49:52 +02:00
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/*
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basic, incomplete SSP160x (SSP1601?) interpreter
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with SVP memory controller emu
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(c) Copyright 2008, Grazvydas "notaz" Ignotas
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Free for non-commercial use.
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For commercial use, separate licencing terms must be obtained.
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Modified for Genesis Plus GX (Eke-Eke): added BIG ENDIAN support, fixed addr/code inversion
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*/
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#ifndef _SSP16_H_
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#define _SSP16_H_
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/* emulation event logging (from Picodrive) */
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2012-01-15 20:59:13 +01:00
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#ifdef LOG_SVP
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2011-07-14 00:49:52 +02:00
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#define EL_SVP 0x00004000 /* SVP stuff */
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#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */
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#define elprintf(w,f,...) error("%d(%d): " f "\n",frame_count,v_counter,##__VA_ARGS__);
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#endif
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/* register names */
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enum {
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SSP_GR0, SSP_X, SSP_Y, SSP_A,
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SSP_ST, SSP_STACK, SSP_PC, SSP_P,
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SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
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SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
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};
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typedef union
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{
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unsigned int v;
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struct {
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#ifdef LSB_FIRST
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unsigned short l;
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unsigned short h;
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#else
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unsigned short h;
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unsigned short l;
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#endif
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2012-01-15 20:59:13 +01:00
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} byte;
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2011-07-14 00:49:52 +02:00
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} ssp_reg_t;
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typedef struct
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{
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union {
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2012-01-15 20:59:13 +01:00
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unsigned short RAM[256*2]; /* 2 internal RAM banks */
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2011-07-14 00:49:52 +02:00
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struct {
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unsigned short RAM0[256];
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unsigned short RAM1[256];
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2012-01-15 20:59:13 +01:00
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} bank;
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} mem;
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ssp_reg_t gr[16]; /* general registers */
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2011-07-14 00:49:52 +02:00
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union {
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2012-01-15 20:59:13 +01:00
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unsigned char r[8]; /* BANK pointers */
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2011-07-14 00:49:52 +02:00
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struct {
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unsigned char r0[4];
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unsigned char r1[4];
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2012-01-15 20:59:13 +01:00
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} bank;
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} ptr;
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2011-07-14 00:49:52 +02:00
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unsigned short stack[6];
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2012-01-15 20:59:13 +01:00
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unsigned int pmac[2][6]; /* read/write modes/addrs for PM0-PM5 */
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#define SSP_PMC_HAVE_ADDR 0x0001 /* address written to PMAC, waiting for mode */
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#define SSP_PMC_SET 0x0002 /* PMAC is set */
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#define SSP_HANG 0x1000 /* 68000 hangs SVP */
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#define SSP_WAIT_PM0 0x2000 /* bit1 in PM0 */
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#define SSP_WAIT_30FE06 0x4000 /* ssp tight loops on 30FE08 to become non-zero */
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#define SSP_WAIT_30FE08 0x8000 /* same for 30FE06 */
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#define SSP_WAIT_MASK 0xf000
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2011-07-14 00:49:52 +02:00
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unsigned int emu_status;
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unsigned int pad[30];
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} ssp1601_t;
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void ssp1601_reset(ssp1601_t *ssp);
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void ssp1601_run(int cycles);
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#endif
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