2008-08-07 14:26:07 +02:00
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#ifndef Z80_H_
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#define Z80_H_
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#include "cpuintrf.h"
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enum {
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Z80_PC=1, Z80_SP, Z80_A, Z80_B,
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Z80_C, Z80_D, Z80_E, Z80_H, Z80_L,
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Z80_AF, Z80_BC, Z80_DE, Z80_HL,
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Z80_IX, Z80_IY, Z80_AF2, Z80_BC2, Z80_DE2, Z80_HL2,
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Z80_R, Z80_I, Z80_IM, Z80_IFF1, Z80_IFF2, Z80_HALT,
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Z80_DC0, Z80_DC1, Z80_DC2, Z80_DC3
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};
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enum {
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Z80_TABLE_op,
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Z80_TABLE_cb,
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Z80_TABLE_ed,
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Z80_TABLE_xy,
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Z80_TABLE_xycb,
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Z80_TABLE_ex /* cycles counts for taken jr/jp/call and interrupt latency (rst opcodes) */
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};
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/****************************************************************************/
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/* The Z80 registers. HALT is set to 1 when the CPU is halted, the refresh */
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/* register is calculated as follows: refresh=(Z80.r&127)|(Z80.r2&128) */
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/****************************************************************************/
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typedef struct
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{
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PAIR prvpc,pc,sp,af,bc,de,hl,ix,iy;
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PAIR af2,bc2,de2,hl2;
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UINT8 r,r2,iff1,iff2,halt,im,i;
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UINT8 nmi_state; /* nmi line state */
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UINT8 nmi_pending; /* nmi pending */
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UINT8 irq_state; /* irq line state */
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UINT8 after_ei; /* are we in the EI shadow? */
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const struct z80_irq_daisy_chain *daisy;
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int (*irq_callback)(int irqline);
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} Z80_Regs;
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extern int z80_ICount;
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extern Z80_Regs Z80;
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void z80_init(int index, int clock, const void *config, int (*irqcallback)(int));
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void z80_reset (void);
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void z80_exit (void);
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int z80_execute(int cycles);
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void z80_burn(int cycles);
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void z80_get_context (void *dst);
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void z80_set_context (void *src);
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void z80_set_irq_line(int irqline, int state);
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unsigned int cpu_readport16(unsigned int port);
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void cpu_writeport16(unsigned int port, unsigned int data);
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unsigned int cpu_readmem16(unsigned int address);
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void cpu_writemem16(unsigned int address, unsigned int data);
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#endif
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