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https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-12-27 19:51:48 +01:00
[VDP]
.improved FIFO timings accuracy (fixes Sol Deace intro) .code cleanup
This commit is contained in:
ekeeke31
parent
68ceeb3b8c
commit
0794c4a5d6
88
source/vdp.c
88
source/vdp.c
@ -127,12 +127,12 @@ static const uint32 dma_rates[16] = {
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/*--------------------------------------------------------------------------*/
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/* Functions prototype */
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/*--------------------------------------------------------------------------*/
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static inline void fifo_update();
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static inline void data_w(unsigned int data);
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static inline void reg_w(unsigned int r, unsigned int d);
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static inline void dma_copy(void);
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static inline void dma_vbus (void);
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static inline void dma_fill(unsigned int data);
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static void fifo_update();
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static void data_w(unsigned int data);
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static void reg_w(unsigned int r, unsigned int d);
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static void dma_copy(void);
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static void dma_vbus (void);
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static void dma_fill(unsigned int data);
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/*--------------------------------------------------------------------------*/
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/* Init, reset, shutdown functions */
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@ -172,7 +172,7 @@ void vdp_reset(void)
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interlaced = 0;
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fifo_write_cnt = 0;
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fifo_lastwrite = 0;
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fifo_latency = 192; /* default FIFO timings */
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fifo_latency = 190; /* default FIFO timings */
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status = vdp_pal | 0x0200; /* FIFO empty */
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@ -248,7 +248,7 @@ void vdp_restore(uint8 *vdp_regs)
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bitmap.viewport.changed = 1;
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/* restore FIFO timings */
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fifo_latency = (reg[12] & 1) ? 192 : 210;
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fifo_latency = (reg[12] & 1) ? 190 : 214;
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if ((code & 0x0F) == 0x01)
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fifo_latency = fifo_latency * 2;
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@ -387,22 +387,21 @@ void vdp_ctrl_w(unsigned int data)
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}
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/*
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FIFO emulation (Chaos Engine/Soldier of Fortune, Double Clutch)
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---------------------------------------------------------------
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HDISP is 2560 mcycles (same in both modes)
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FIFO emulation (Chaos Engine/Soldier of Fortune, Double Clutch, Sol Deace)
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--------------------------------------------------------------------------
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CPU access per line is limited during active display:
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H32: 16 access --> 2560/16 = 160 cycles between access
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H40: 18 access --> 2560/18 = 142 cycles between access
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H32: 16 access --> 3420/16 = ~214 Mcycles between access
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H40: 18 access --> 3420/18 = ~190 Mcycles between access
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FIFO access seems to require some additional cyles (VDP latency).
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This is an approximation, on real hardware, the delay between access is
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more likely 16 pixels (128 or 160 Mcycles) with no access allowed during
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HBLANK (~860 Mcycles), H40 mode being probably a little more restricted.
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Also note that VRAM access are byte wide, so one VRAM write (word)
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takes twice CPU cycles.
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Each VRAM access is byte wide, so one VRAM write (word) need twice cycles.
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*/
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fifo_latency = (reg[12] & 1) ? 192 : 210;
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fifo_latency = (reg[12] & 1) ? 190 : 214;
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if ((code & 0x0F) == 0x01)
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fifo_latency = fifo_latency * 2;
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}
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@ -432,7 +431,7 @@ unsigned int vdp_ctrl_r(void)
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if ((status & 2) && !dma_length && (mcycles_68k >= dma_endCycles))
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status &= 0xFFFD;
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uint32 temp = status;
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unsigned int temp = status;
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/* display OFF: VBLANK flag is set */
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if (!(reg[1] & 0x40))
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@ -554,6 +553,12 @@ unsigned int vdp_data_r(void)
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error("[%d(%d)][%d(%d)] VSRAM 0x%x read -> 0x%x (%x)\n", v_counter, mcycles_68k/MCYCLES_PER_LINE, mcycles_68k, mcycles_68k%MCYCLES_PER_LINE, addr, temp, m68k_get_reg (NULL, M68K_REG_PC));
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#endif
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break;
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#ifdef LOGVDP
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default:
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error("[%d(%d)][%d(%d)] Unknown (%d) 0x%x read (%x)\n", v_counter, mcycles_68k/MCYCLES_PER_LINE, mcycles_68k, mcycles_68k%MCYCLES_PER_LINE, code, addr, m68k_get_reg (NULL, M68K_REG_PC));
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break;
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#endif
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}
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/* Increment address register */
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@ -616,12 +621,12 @@ int vdp_int_ack_callback(int int_level)
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/*--------------------------------------------------------------------------*/
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/* FIFO emulation */
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/*--------------------------------------------------------------------------*/
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static inline void fifo_update()
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static void fifo_update()
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{
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if (fifo_write_cnt > 0)
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{
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/* update FIFO reads */
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uint32 fifo_read = ((mcycles_68k - fifo_lastwrite) / fifo_latency);
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int fifo_read = ((mcycles_68k - fifo_lastwrite) / fifo_latency);
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if (fifo_read > 0)
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{
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fifo_write_cnt -= fifo_read;
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@ -649,16 +654,14 @@ static inline void fifo_update()
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/*--------------------------------------------------------------------------*/
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/* Memory access functions */
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/*--------------------------------------------------------------------------*/
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static inline void data_w(unsigned int data)
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static void data_w(unsigned int data)
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{
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switch (code & 0x0F)
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{
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case 0x01: /* VRAM */
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#ifdef LOGVDP
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error("[%d(%d)][%d(%d)] VRAM 0x%x write -> 0x%x (%x)\n", v_counter, mcycles_68k/MCYCLES_PER_LINE, mcycles_68k, mcycles_68k%MCYCLES_PER_LINE, addr, data, m68k_get_reg (NULL, M68K_REG_PC));
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#endif
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/* Byte-swap data if A0 is set */
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if (addr & 1)
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data = ((data >> 8) | (data << 8)) & 0xFFFF;
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@ -724,19 +727,25 @@ static inline void data_w(unsigned int data)
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#endif
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*(uint16 *) &vsram[(addr & 0x7E)] = data;
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break;
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#ifdef LOGVDP
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default:
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error("[%d(%d)][%d(%d)] Unknown (%d) 0x%x write -> 0x%x (%x)\n", v_counter, mcycles_68k/MCYCLES_PER_LINE, mcycles_68k, mcycles_68k%MCYCLES_PER_LINE, code, addr, data, m68k_get_reg (NULL, M68K_REG_PC));
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break;
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#endif
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}
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/* Increment address register */
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addr += reg[15];
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}
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static inline void reg_w(unsigned int r, unsigned int d)
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static void reg_w(unsigned int r, unsigned int d)
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{
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#ifdef LOGVDP
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error("[%d(%d)][%d(%d)] VDP register %d write -> 0x%x (%x)\n", v_counter, mcycles_68k/MCYCLES_PER_LINE, mcycles_68k, mcycles_68k%MCYCLES_PER_LINE, r, d, m68k_get_reg (NULL, M68K_REG_PC));
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#endif
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/* See if Mode 4 (SMS mode) is enabled
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/* Mode 4 (SMS mode) is enabled
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According to official doc, VDP registers #11 to #23 can not be written unless bit2 in register #1 is set
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Fix Captain Planet & Avengers (Alt version), Bass Master Classic Pro Edition (they incidentally activate Mode 4)
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*/
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@ -921,7 +930,7 @@ static inline void reg_w(unsigned int r, unsigned int d)
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bitmap.viewport.x = 16;
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/* Update fifo timings */
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fifo_latency = ((code & 0x0F) == 0x01) ? 384 : 192;
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fifo_latency = 190;
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}
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else
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{
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@ -940,8 +949,11 @@ static inline void reg_w(unsigned int r, unsigned int d)
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bitmap.viewport.x = 12;
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/* Update fifo timings */
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fifo_latency = ((code & 0x0F) == 0x01) ? 420 : 210;
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fifo_latency = 214;
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}
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if ((code & 0x0F) == 0x01)
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fifo_latency *= 2;
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/* Update viewport */
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bitmap.viewport.changed = 1;
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@ -995,11 +1007,11 @@ static inline void reg_w(unsigned int r, unsigned int d)
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- see how source addr is affected
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(can it make high source byte inc?)
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*/
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static inline void dma_copy(void)
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static void dma_copy(void)
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{
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int name;
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uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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uint32 source = (reg[22] << 8 | reg[21]) & 0xFFFF;
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unsigned int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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unsigned int source = (reg[22] << 8 | reg[21]) & 0xFFFF;
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if (!length)
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length = 0x10000;
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@ -1025,12 +1037,12 @@ static inline void dma_copy(void)
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}
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/* 68K Copy to VRAM, VSRAM or CRAM */
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static inline void dma_vbus (void)
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static void dma_vbus (void)
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{
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uint32 source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE;
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uint32 base = source;
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uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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uint32 temp;
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unsigned int source = ((reg[23] & 0x7F) << 17 | reg[22] << 9 | reg[21] << 1) & 0xFFFFFE;
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unsigned int base = source;
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unsigned int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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uint16 temp;
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if (!length)
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length = 0x10000;
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@ -1098,10 +1110,10 @@ static inline void dma_vbus (void)
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}
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/* VRAM FILL */
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static inline void dma_fill(unsigned int data)
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static void dma_fill(unsigned int data)
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{
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int name;
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uint32 length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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unsigned int length = (reg[20] << 8 | reg[19]) & 0xFFFF;
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if (!length)
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length = 0x10000;
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