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|Core/VDP] fixed inverted H32 & H40 modes HBLANK flag timings
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@ -1986,8 +1986,8 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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fifo_timing = (int *)fifo_timing_h40;
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fifo_timing = (int *)fifo_timing_h40;
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/* HBLANK flag timings */
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/* HBLANK flag timings */
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hblank_start_cycle = HBLANK_H32_START_MCYCLE;
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hblank_start_cycle = HBLANK_H40_START_MCYCLE;
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hblank_end_cycle = HBLANK_H32_END_MCYCLE;
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hblank_end_cycle = HBLANK_H40_END_MCYCLE;
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}
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}
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else
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else
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{
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{
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@ -2010,8 +2010,8 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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fifo_timing = (int *)fifo_timing_h32;
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fifo_timing = (int *)fifo_timing_h32;
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/* HBLANK flag timings */
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/* HBLANK flag timings */
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hblank_start_cycle = HBLANK_H40_START_MCYCLE;
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hblank_start_cycle = HBLANK_H32_START_MCYCLE;
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hblank_end_cycle = HBLANK_H40_END_MCYCLE;
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hblank_end_cycle = HBLANK_H32_END_MCYCLE;
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}
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}
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/* Active screen width modified during VBLANK will be applied on upcoming frame */
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/* Active screen width modified during VBLANK will be applied on upcoming frame */
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