mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-04 18:05:06 +01:00
[Core/VDP] implemented proper FIFO ring-buffer & unused bits behavior on CRAM/VSRAM reads (verified on real hardware)
This commit is contained in:
EkeEke
twinaphex
parent
1b0db486e7
commit
16b00f9368
@ -51,7 +51,7 @@ int state_load(unsigned char *state)
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return 0;
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}
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/* version check (1.7.1 and above only) */
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/* version check (keep compatibility with previous & current state version) */
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if ((version[11] < 0x31) || (version[13] < 0x37) || (version[15] < 0x31))
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{
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return 0;
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@ -110,7 +110,7 @@ int state_load(unsigned char *state)
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}
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/* VDP */
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bufferptr += vdp_context_load(&state[bufferptr]);
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bufferptr += vdp_context_load(&state[bufferptr], version[15]);
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/* SOUND */
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bufferptr += sound_context_load(&state[bufferptr]);
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121
core/vdp_ctrl.c
121
core/vdp_ctrl.c
@ -136,7 +136,8 @@ static uint16 dma_src; /* DMA source address */
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static uint16 dmafill; /* DMA Fill setup */
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static uint32 dma_endCycles; /* 68k cycles to DMA end */
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static int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
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static uint16 fifo[4]; /* FIFO buffer */
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static uint16 fifo[4]; /* FIFO ring-buffer */
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static int fifo_idx; /* FIFO write index */
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static int fifo_byte_access; /* FIFO byte access flag */
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static uint32 fifo_cycles; /* FIFO next access cycle */
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@ -231,6 +232,7 @@ void vdp_reset(void)
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fifo_write_cnt = 0;
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fifo_cycles = 0;
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fifo_slots = 0;
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fifo_idx = 0;
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cached_write = -1;
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fifo_byte_access = 1;
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@ -312,16 +314,16 @@ void vdp_reset(void)
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parse_satb = parse_satb_m4;
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}
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/* 68k bus access mode (Mode 4 by default) */
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/* default 68k bus interface (Mega Drive VDP only) */
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vdp_68k_data_w = vdp_68k_data_w_m4;
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vdp_68k_data_r = vdp_68k_data_r_m4;
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/* Z80 bus access mode */
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/* default Z80 bus interface */
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switch (system_hw)
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{
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case SYSTEM_SG:
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{
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/* SG-1000 port access */
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/* SG-1000 VDP (TMS99xx) */
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vdp_z80_data_w = vdp_z80_data_w_sg;
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vdp_z80_data_r = vdp_z80_data_r_m4;
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break;
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@ -329,7 +331,7 @@ void vdp_reset(void)
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case SYSTEM_GG:
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{
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/* Game Gear port access */
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/* Game Gear VDP */
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vdp_z80_data_w = vdp_z80_data_w_gg;
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vdp_z80_data_r = vdp_z80_data_r_m4;
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break;
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@ -340,7 +342,7 @@ void vdp_reset(void)
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case SYSTEM_SMS2:
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case SYSTEM_GGMS:
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{
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/* Master System port access */
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/* Master System or Game Gear (in MS compatibility mode) VDP */
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vdp_z80_data_w = vdp_z80_data_w_ms;
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vdp_z80_data_r = vdp_z80_data_r_m4;
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break;
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@ -348,7 +350,7 @@ void vdp_reset(void)
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default:
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{
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/* Genesis port access */
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/* Mega Drive VDP (in MS compatibility mode) */
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vdp_z80_data_w = vdp_z80_data_w_m4;
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vdp_z80_data_r = vdp_z80_data_r_m4;
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break;
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@ -361,7 +363,7 @@ void vdp_reset(void)
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/* 16k address decoding by default (Magical Kid Wiz) */
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vdp_reg_w(1, 0x80, 0);
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/* no H-INT on TMS9918 */
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/* no H-INT on TMS99xx */
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vdp_reg_w(10, 0xFF, 0);
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}
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@ -418,6 +420,8 @@ int vdp_context_save(uint8 *state)
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save_param(&pending, sizeof(pending));
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save_param(&status, sizeof(status));
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save_param(&dmafill, sizeof(dmafill));
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save_param(&fifo_idx, sizeof(fifo_idx));
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save_param(&fifo, sizeof(fifo));
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save_param(&hint_pending, sizeof(hint_pending));
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save_param(&vint_pending, sizeof(vint_pending));
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save_param(&dma_length, sizeof(dma_length));
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@ -427,7 +431,7 @@ int vdp_context_save(uint8 *state)
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return bufferptr;
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}
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int vdp_context_load(uint8 *state)
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int vdp_context_load(uint8 *state, uint8 version)
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{
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int i, bufferptr = 0;
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uint8 temp_reg[0x20];
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@ -473,13 +477,29 @@ int vdp_context_load(uint8 *state)
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load_param(&code, sizeof(code));
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load_param(&pending, sizeof(pending));
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load_param(&status, sizeof(status));
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load_param(&dmafill, sizeof(dmafill));
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/* 1.7.1 state compatibility */
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if (version < 0x35)
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{
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uint16 temp;
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load_param(&temp, 2);
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dmafill = temp >> 8;
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temp &= 0xff;
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fifo_idx = 0;
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fifo[0] = fifo[1] = fifo[2] = fifo[3] = (temp << 8) | temp;
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}
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else
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{
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load_param(&dmafill, sizeof(dmafill));
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load_param(&fifo_idx, sizeof(fifo_idx));
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load_param(&fifo, sizeof(fifo));
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}
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load_param(&hint_pending, sizeof(hint_pending));
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load_param(&vint_pending, sizeof(vint_pending));
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load_param(&dma_length, sizeof(dma_length));
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load_param(&dma_type, sizeof(dma_type));
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load_param(&dma_src, sizeof(dma_src));
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load_param(&cached_write, sizeof(cached_write));
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/* restore FIFO byte access flag */
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@ -528,7 +548,7 @@ int vdp_context_load(uint8 *state)
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/*--------------------------------------------------------------------------*/
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/* DMA update function */
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/* DMA update function (Mega Drive VDP only) */
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/*--------------------------------------------------------------------------*/
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void vdp_dma_update(unsigned int cycles)
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@ -1097,7 +1117,7 @@ void vdp_sms_ctrl_w(unsigned int data)
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}
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}
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/* TMS9918 (SG-1000) VDP control port specific */
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/* SG-1000 VDP (TMS99xx) control port specific */
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void vdp_tms_ctrl_w(unsigned int data)
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{
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if(pending == 0)
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@ -2140,7 +2160,13 @@ static void vdp_fifo_update(unsigned int cycles)
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static void vdp_bus_w(unsigned int data)
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{
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/* Check destination code */
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/* write data to next FIFO entry */
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fifo[fifo_idx] = data;
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/* increment FIFO write pointer */
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fifo_idx = (fifo_idx + 1) & 3;
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/* Check destination code (CD0-CD3) */
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switch (code & 0x0F)
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{
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case 0x01: /* VRAM */
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@ -2260,7 +2286,7 @@ static void vdp_bus_w(unsigned int data)
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/*--------------------------------------------------------------------------*/
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/* 68k data port access functions (Genesis mode) */
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/* 68k bus interface (Mega Drive VDP only) */
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/*--------------------------------------------------------------------------*/
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static void vdp_68k_data_w_m4(unsigned int data)
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@ -2434,11 +2460,12 @@ static unsigned int vdp_68k_data_r_m5(void)
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/* Clear pending flag */
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pending = 0;
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switch (code & 0x0F)
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/* Check destination code (CD0-CD3) & CD4 */
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switch (code & 0x1F)
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{
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case 0x00: /* VRAM */
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case 0x00:
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{
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/* Read data */
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/* read two bytes from VRAM */
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data = *(uint16 *)&vram[addr & 0xFFFE];
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#ifdef LOGVDP
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@ -2447,10 +2474,23 @@ static unsigned int vdp_68k_data_r_m5(void)
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break;
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}
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case 0x04: /* VSRAM */
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case 0x04:
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{
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/* Read data */
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data = *(uint16 *)&vsram[addr & 0x7E];
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/* VSRAM index */
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int index = addr & 0x7E;
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/* Check against VSRAM max size (80 x 11-bits) */
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if (index >= 0x50)
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{
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/* Wrap to address 0 (TODO: check if still true with Genesis 3 model) */
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index = 0;
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}
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/* Read 11-bit word from VSRAM */
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data = *(uint16 *)&vsram[index] & 0x7FF;
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/* Unused bits are set using data from next available FIFO entry */
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data |= (fifo[fifo_idx] & ~0x7FF);
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#ifdef LOGVDP
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error("[%d(%d)][%d(%d)] VSRAM 0x%x read -> 0x%x (%x)\n", v_counter, m68k.cycles/MCYCLES_PER_LINE-1, m68k.cycles, m68k.cycles%MCYCLES_PER_LINE, addr, data, m68k_get_reg(M68K_REG_PC));
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@ -2458,24 +2498,30 @@ static unsigned int vdp_68k_data_r_m5(void)
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break;
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}
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case 0x08: /* CRAM */
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case 0x08:
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{
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/* Read data */
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/* Read 9-bit word from CRAM */
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data = *(uint16 *)&cram[addr & 0x7E];
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/* Unpack 9-bit CRAM data (BBBGGGRRR) to 16-bit bus data (BBB0GGG0RRR0) */
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data = ((data & 0x1C0) << 3) | ((data & 0x038) << 2) | ((data & 0x007) << 1);
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/* Unused bits are set using data from next available FIFO entry */
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data |= (fifo[fifo_idx] & ~0xEEE);
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#ifdef LOGVDP
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error("[%d(%d)][%d(%d)] CRAM 0x%x read -> 0x%x (%x)\n", v_counter, m68k.cycles/MCYCLES_PER_LINE-1, m68k.cycles, m68k.cycles%MCYCLES_PER_LINE, addr, data, m68k_get_reg(M68K_REG_PC));
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#endif
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break;
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}
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case 0x0c: /* undocumented 8-bit VRAM read (cf. http://gendev.spritesmind.net/forum/viewtopic.php?t=790) */
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case 0x0c: /* undocumented 8-bit VRAM read */
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{
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/* Read data (MSB forced to zero) */
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data = *(uint16 *)&vram[addr & 0xFFFE] & 0xff;
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/* Read one byte from VRAM adjacent address */
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data = READ_BYTE(vram, addr ^ 1);
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/* Unused bits are set using data from next available FIFO entry */
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data |= (fifo[fifo_idx] & ~0xFF);
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#ifdef LOGVDP
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error("[%d(%d)][%d(%d)] 8-bit VRAM 0x%x read -> 0x%x (%x)\n", v_counter, m68k.cycles/MCYCLES_PER_LINE-1, m68k.cycles, m68k.cycles%MCYCLES_PER_LINE, addr, data, m68k_get_reg(M68K_REG_PC));
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@ -2485,7 +2531,7 @@ static unsigned int vdp_68k_data_r_m5(void)
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default:
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{
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/* Invalid code value */
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/* Invalid code value (normally locks VDP, hard reset required) */
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#ifdef LOGERROR
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error("[%d(%d)][%d(%d)] Invalid (%d) 0x%x read (%x)\n", v_counter, m68k.cycles/MCYCLES_PER_LINE-1, m68k.cycles, m68k.cycles%MCYCLES_PER_LINE, code, addr, m68k_get_reg(M68K_REG_PC));
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#endif
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@ -2502,7 +2548,7 @@ static unsigned int vdp_68k_data_r_m5(void)
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/*--------------------------------------------------------------------------*/
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/* Z80 data port access functions (Master System compatibility mode) */
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/* Z80 bus interface (Mega Drive VDP in Master System compatibility mode) */
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/*--------------------------------------------------------------------------*/
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static void vdp_z80_data_w_m4(unsigned int data)
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@ -2562,7 +2608,11 @@ static void vdp_z80_data_w_m5(unsigned int data)
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/* Clear pending flag */
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pending = 0;
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/* Check destination code */
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/* Push byte into FIFO */
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fifo[fifo_idx] = data << 8;
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fifo_idx = (fifo_idx + 1) & 3;
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/* Check destination code (CD0-CD3) */
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switch (code & 0x0F)
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{
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case 0x01: /* VRAM */
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@ -2690,7 +2740,8 @@ static unsigned int vdp_z80_data_r_m5(void)
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/* Clear pending flag */
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pending = 0;
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switch (code & 0x0F)
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/* Check destination code (CD0-CD3) & CD4 */
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switch (code & 0x1F)
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{
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case 0x00: /* VRAM */
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{
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@ -2734,7 +2785,7 @@ static unsigned int vdp_z80_data_r_m5(void)
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/*-----------------------------------------------------------------------------*/
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/* VDP specific data port access functions (Master System, Game Gear, SG-1000) */
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/* Z80 bus interface (Master System, Game Gear & SG-1000 VDP) */
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/*-----------------------------------------------------------------------------*/
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static void vdp_z80_data_w_ms(unsigned int data)
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@ -2746,10 +2797,11 @@ static void vdp_z80_data_w_ms(unsigned int data)
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{
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int index;
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/* check if we are already on next line */
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/* Check if we are already on next line */
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int line = (lines_per_frame + (Z80.cycles / MCYCLES_PER_LINE) - 1) % lines_per_frame;
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if ((line > v_counter) && (line < bitmap.viewport.h) && !(work_ram[0x1ffb] & cart.special))
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{
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/* Render next line */
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v_counter = line;
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render_line(line);
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}
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@ -2813,10 +2865,11 @@ static void vdp_z80_data_w_gg(unsigned int data)
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{
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int index;
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/* check if we are already on next line*/
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/* Check if we are already on next line*/
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int line = (lines_per_frame + (Z80.cycles / MCYCLES_PER_LINE) - 1) % lines_per_frame;
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if ((line > v_counter) && (line < bitmap.viewport.h) && !(work_ram[0x1ffb] & cart.special))
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{
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/* Render next line */
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v_counter = line;
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render_line(line);
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}
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@ -2907,7 +2960,7 @@ static void vdp_z80_data_w_sg(unsigned int data)
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}
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/*--------------------------------------------------------------------------*/
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/* DMA operations */
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/* DMA operations (Mega Drive VDP only) */
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/*--------------------------------------------------------------------------*/
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/* DMA from 68K bus: $000000-$7FFFFF (external area) */
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@ -90,7 +90,7 @@ extern unsigned int (*vdp_z80_data_r)(void);
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extern void vdp_init(void);
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extern void vdp_reset(void);
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extern int vdp_context_save(uint8 *state);
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extern int vdp_context_load(uint8 *state);
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extern int vdp_context_load(uint8 *state, uint8 version);
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extern void vdp_dma_update(unsigned int cycles);
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extern void vdp_68k_ctrl_w(unsigned int data);
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extern void vdp_z80_ctrl_w(unsigned int data);
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