mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-10 21:05:12 +01:00
This commit is contained in:
commit
29ee7e1244
@ -20,10 +20,11 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
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||||
* improved savestate format
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* improved Sub-CPU synchronization with Main-CPU (fixes "Soul Star")
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* improved Main-CPU & Sub-CPU idle loop detection (fixes "Super League CD")
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||||
* disabled 68k and Z80 access to PRG-RAM when SUB-CPU is running (fixes USA version of Dungeon Explorer )
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||||
* disabled 68k and Z80 access to PRG-RAM when SUB-CPU is running (fixes "Dungeon Explorer")
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* disabled CD hardware reset on Soft-Reset (verified on real hardware)
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* fixed DATA track minimal length (fixes BIOS refusing to boot small homebrew demos)
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* fixed CDD "no disc" status code (fixes boot sequence loading time when no disc is loaded)
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* fixed AUDIO tracks length calculation when using separated files (WAV/OGG/BIN) with INDEX pause defined in CUE file
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* fixed OGG file seeking when using with CUE file
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* fixed PRG-RAM access from MAIN-CPU side on system reset
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* fixed state loading bug when SUB-CPU interrupt is pending
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@ -76,7 +77,8 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
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* added Sega Graphic Board support (thanks to SMS Power)
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* added Master Tap emulation (multi-player support in Boom homebrew)
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* added gamepad type auto-detection
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* added support for XE-1AP analog controller on both ports
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* added support for XE-1AP controller on both ports
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* improved XE-1AP controller emulation
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* improved HVC latch behavior for gun emulation (fixes "Gunfight - 3 in 1" randomization when using Justifier)
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* fixed TeamPlayer emulation (fixes multitap detection in Gauntlet 4)
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@ -180,6 +180,7 @@ static const md_entry_t rom_database[] =
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/* Thunderbolt II (uses 16-bits reads) */
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{0x0000,0x1585,0x40,0x40,{{0x55,0x0f,0xaa,0xf0},{0xffffff,0xffffff,0xffffff,0xffffff},{0x400000,0x400002,0x400004,0x400006},0,0,NULL,NULL,default_regs_r_16,NULL}},
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/* Chaoji Puke - Super Poker (correct ROM dump, original release is an overdump) */
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{0xffff,0xd7b0,0x40,0x40,{{0x55,0x0f,0xaa,0xf0},{0xffffff,0xffffff,0xffffff,0xffffff},{0x400000,0x400002,0x400004,0x400006},0,0,NULL,NULL,default_regs_r,NULL}},
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/* Super Bubble Bobble */
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@ -569,18 +570,18 @@ void md_cart_init(void)
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if (strstr(rominfo.consoletype,"SEGA SSF"))
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{
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/* Everdrive extended SSF mapper */
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cart.hw.bankshift = 1;
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/* specific !TIME handler */
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cart.hw.time_w = mapper_512k_w;
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/* cartridge ROM mapping is reinitialized on /VRES */
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cart.hw.bankshift = 1;
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}
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else if (strstr(rominfo.domestic,"SUPER STREET FIGHTER2"))
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{
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/* SSF2 mapper */
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cart.hw.bankshift = 1;
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/* specific !TIME handler */
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cart.hw.time_w = mapper_ssf2_w;
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/* cartridge ROM mapping is reinitialized on /VRES */
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cart.hw.bankshift = 1;
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}
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else if (strstr(rominfo.product,"T-5740"))
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{
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@ -605,6 +606,18 @@ void md_cart_init(void)
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/* no !TIME handler */
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cart.hw.time_w = m68k_unused_8_w;
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/* cartridge ROM is mapped to $3C0000-$3FFFFF on reset */
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for (i=0x3c; i<0x40; i++)
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{
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m68k.memory_map[i].base = cart.rom + (i << 16);
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m68k.memory_map[i].read8 = NULL;
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m68k.memory_map[i].read16 = NULL;
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m68k.memory_map[i].write8 = m68k_unused_8_w;
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m68k.memory_map[i].write16 = m68k_unused_16_w;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = m68k_unused_8_w;
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}
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}
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else if (strstr(rominfo.ROMType,"SF") && strstr(rominfo.product,"002"))
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{
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@ -627,13 +640,13 @@ void md_cart_init(void)
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cart.hw.time_r = mapper_sf004_r;
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cart.hw.time_w = m68k_unused_8_w;
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/* first 256K ROM bank is initially mirrored into $000000-$1FFFFF */
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/* first 256K ROM bank is mirrored into $000000-$1FFFFF on reset */
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for (i=0x00; i<0x20; i++)
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{
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m68k.memory_map[i].base = cart.rom + ((i & 0x03) << 16);
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}
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/* 32K static RAM is mapped to $200000-$2FFFFF (disabled on startup) */
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/* 32K static RAM mapped to $200000-$2FFFFF is disabled on reset */
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for (i=0x20; i<0x30; i++)
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{
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m68k.memory_map[i].base = sram.sram;
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@ -929,7 +942,6 @@ static void mapper_512k_w(uint32 address, uint32 data)
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/* 512K ROM paging */
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uint8 *src = cart.rom + (data << 19);
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/* cartridge area ($000000-$3FFFFF) is divided into 8 x 512K banks */
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address = (address << 2) & 0x38;
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@ -582,8 +582,8 @@ int cdd_load(char *filename, char *header)
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}
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else
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{
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/* current track start time (based on previous track end time + current file absolute time + PREGAP length) */
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cdd.toc.tracks[cdd.toc.last].start = cdd.toc.end + bb + ss*75 + mm*60*75 + pregap;
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/* current file start time (based on previous track end time + PREGAP length) */
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cdd.toc.tracks[cdd.toc.last].start = cdd.toc.end + pregap;
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/* adjust current track file read offset with previous track end time (only used for AUDIO track) */
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cdd.toc.tracks[cdd.toc.last].offset += cdd.toc.end * 2352;
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@ -630,6 +630,9 @@ int cdd_load(char *filename, char *header)
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fseek(cdd.toc.tracks[cdd.toc.last].fd, 0, SEEK_SET);
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}
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/* adjust track start time (based on current file start time + index absolute time) */
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cdd.toc.tracks[cdd.toc.last].start += (bb + ss*75 + mm*60*75);
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/* update TOC end */
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cdd.toc.end = cdd.toc.tracks[cdd.toc.last].end;
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}
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@ -1218,7 +1221,7 @@ void cdd_update(void)
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#ifdef LOG_CDD
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error("LBA = %d (track n°%d)(latency=%d)\n", cdd.lba, cdd.index, cdd.latency);
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#endif
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/* seeking disc */
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if (cdd.status == CD_SEEK)
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{
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@ -1230,7 +1233,7 @@ void cdd_update(void)
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}
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/* drive is ready */
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cdd.status = CD_READY;
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cdd.status = CD_PAUSE;
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}
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/* reading disc */
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@ -1460,12 +1463,12 @@ void cdd_process(void)
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/* no audio track playing */
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scd.regs[0x36>>1].byte.h = 0x01;
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/* RS1-RS8 ignored, expects 0x0 (?) in RS0 once */
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scd.regs[0x38>>1].w = 0x0000;
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/* RS1-RS8 ignored, expects 0x0 (drive busy ?) in RS0 once */
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scd.regs[0x38>>1].w = CD_BUSY << 8;
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scd.regs[0x3a>>1].w = 0x0000;
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scd.regs[0x3c>>1].w = 0x0000;
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scd.regs[0x3e>>1].w = 0x0000;
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scd.regs[0x40>>1].w = 0x000f;
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scd.regs[0x40>>1].w = ~CD_BUSY & 0x0f;
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return;
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}
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@ -1765,7 +1768,7 @@ void cdd_process(void)
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scd.regs[0x36>>1].byte.h = 0x01;
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/* update status (RS1-RS8 unchanged) */
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cdd.status = scd.regs[0x38>>1].byte.h = CD_READY;
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cdd.status = scd.regs[0x38>>1].byte.h = CD_PAUSE;
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break;
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}
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@ -1808,7 +1811,7 @@ void cdd_process(void)
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scd.regs[0x36>>1].byte.h = 0x01;
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/* update status (RS1-RS8 unchanged) */
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cdd.status = scd.regs[0x38>>1].byte.h = CD_READY;
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cdd.status = scd.regs[0x38>>1].byte.h = CD_PAUSE;
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break;
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}
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@ -1820,12 +1823,12 @@ void cdd_process(void)
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/* update status */
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cdd.status = cdd.loaded ? CD_STOP : NO_DISC;
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/* RS1-RS8 ignored, expects 0x0 (?) in RS0 once */
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scd.regs[0x38>>1].w = 0x0000;
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/* RS1-RS8 ignored, expects 0x0 (drive busy ?) in RS0 once */
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scd.regs[0x38>>1].w = CD_BUSY << 8;
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scd.regs[0x3a>>1].w = 0x0000;
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scd.regs[0x3c>>1].w = 0x0000;
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scd.regs[0x3e>>1].w = 0x0000;
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scd.regs[0x40>>1].w = 0x000f;
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scd.regs[0x40>>1].w = ~CD_BUSY & 0x0f;
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#ifdef CD_TRAY_CALLBACK
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CD_TRAY_CALLBACK
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@ -49,10 +49,11 @@
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#define cdd scd.cdd_hw
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/* CDD status */
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#define CD_BUSY 0x00
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#define CD_PLAY 0x01
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#define CD_SEEK 0x02
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#define CD_SCAN 0x03
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#define CD_READY 0x04
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#define CD_PAUSE 0x04
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#define CD_OPEN 0x05
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#define CD_STOP 0x09
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#define NO_DISC 0x0B
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@ -2,8 +2,8 @@
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* Genesis Plus
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* Input peripherals support
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2014 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2015 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -2,8 +2,8 @@
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* Genesis Plus
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* Input peripherals support
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*
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* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2014 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 1998-2003 Charles Mac Donald (original code)
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* Copyright (C) 2007-2015 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -102,12 +102,14 @@
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#define INPUT_PICO_RED (0x0010)
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/* XE-1AP specific bitmask */
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#define INPUT_XE_E1 (0x0800)
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#define INPUT_XE_E2 (0x0400)
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#define INPUT_XE_START (0x0200)
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#define INPUT_XE_SELECT (0x0100)
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#define INPUT_XE_A (0x0080)
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#define INPUT_XE_B (0x0040)
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#define INPUT_XE_E1 (0x2000)
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#define INPUT_XE_E2 (0x1000)
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#define INPUT_XE_START (0x0800)
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#define INPUT_XE_SELECT (0x0400)
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#define INPUT_XE_A (0x0200)
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#define INPUT_XE_B (0x0100)
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#define INPUT_XE_A2 (0x0080)
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#define INPUT_XE_B2 (0x0040)
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#define INPUT_XE_C (0x0020)
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#define INPUT_XE_D (0x0010)
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@ -2,7 +2,7 @@
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* Genesis Plus
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* XE-1AP analog controller support
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*
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* Copyright (C) 2011-2014 Eke-Eke (Genesis Plus GX)
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* Copyright (C) 2011-2015 Eke-Eke (Genesis Plus GX)
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*
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* Redistribution and use of this code or any derivative works are permitted
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* provided that the following conditions are met:
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@ -38,6 +38,8 @@
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#include "shared.h"
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#define XE_1AP_LATENCY 3
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static struct
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{
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uint8 State;
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@ -52,109 +54,99 @@ void xe_1ap_reset(int index)
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input.analog[index+1][0] = 128;
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index >>= 2;
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xe_1ap[index].State = 0x40;
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xe_1ap[index].Counter = 0;
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xe_1ap[index].Counter = 11;
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xe_1ap[index].Latency = 0;
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}
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INLINE unsigned char xe_1ap_read(int index)
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{
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unsigned int temp = 0x40;
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unsigned char data;
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unsigned int port = index << 2;
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|
||||
/* Left Stick X & Y analog values (bidirectional) */
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int x = input.analog[port][0];
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||||
int y = input.analog[port][1];
|
||||
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||||
/* Right Stick X or Y value (unidirectional) */
|
||||
int z = input.analog[port+1][0];
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||||
|
||||
/* Buttons status (active low) */
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||||
uint16 pad = ~input.pad[port];
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|
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/* Current internal cycle (0-7) */
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unsigned int cycle = xe_1ap[index].Counter & 7;
|
||||
|
||||
/* Current 4-bit data cycle */
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||||
/* There are eight internal data cycle for each 5 acquisition sequence */
|
||||
/* First 4 return the same 4-bit data, next 4 return next 4-bit data */
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||||
switch (xe_1ap[index].Counter >> 2)
|
||||
/* Current data transfer cycle */
|
||||
switch (xe_1ap[index].Counter)
|
||||
{
|
||||
case 0:
|
||||
temp |= ((pad >> 8) & 0x0F); /* E1 E2 Start Select */
|
||||
case 0: /* E1 E2 Start Select buttons status (active low) */
|
||||
data = (~input.pad[port] >> 10) & 0x0F;
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||||
break;
|
||||
case 1:
|
||||
temp |= ((pad >> 4) & 0x0F); /* A B C D */
|
||||
case 1: /* A/A' B/B' C D buttons status (active low) */
|
||||
data = ((~input.pad[port] >> 4) & 0x0F) & ~((input.pad[port] >> 6) & 0x0C);
|
||||
break;
|
||||
case 2:
|
||||
temp |= ((x >> 4) & 0x0F);
|
||||
case 2: /* CH0 high (Analog Stick Left/Right direction) */
|
||||
data = (input.analog[port][0] >> 4) & 0x0F;
|
||||
break;
|
||||
case 3:
|
||||
temp |= ((y >> 4) & 0x0F);
|
||||
case 3: /* CH1 high (Analog Stick Up/Down direction) */
|
||||
data = (input.analog[port][1] >> 4) & 0x0F;
|
||||
break;
|
||||
case 4:
|
||||
case 4: /* CH2 high (N/A) */
|
||||
data = 0x0;
|
||||
break;
|
||||
case 5:
|
||||
temp |= ((z >> 4) & 0x0F);
|
||||
case 5: /* CH3 high (Throttle vertical or horizontal direction) */
|
||||
data = (input.analog[port+1][0] >> 4) & 0x0F;
|
||||
break;
|
||||
case 6:
|
||||
temp |= (x & 0x0F);
|
||||
case 6: /* CH0 low (Analog Stick Left/Right direction) */
|
||||
data = input.analog[port][0] & 0x0F;
|
||||
break;
|
||||
case 7:
|
||||
temp |= (y & 0x0F);
|
||||
case 7: /* CH1 low (Analog Stick Up/Down direction)*/
|
||||
data = input.analog[port][1] & 0x0F;
|
||||
break;
|
||||
case 8:
|
||||
case 8: /* CH2 low (N/A) */
|
||||
data = 0x0;
|
||||
break;
|
||||
case 9:
|
||||
temp |= (z & 0x0F);
|
||||
case 9: /* CH3 low (Throttle vertical or horizontal direction) */
|
||||
data = input.analog[port+1][0] & 0x0F;
|
||||
break;
|
||||
case 10: /* A B A' B' buttons status (active low) */
|
||||
data = (~input.pad[port] >> 6) & 0x0F;
|
||||
break;
|
||||
default: /* N/A */
|
||||
data = 0x0F;
|
||||
break;
|
||||
}
|
||||
|
||||
/* TL indicates which part of data is returned (0=1st part, 1=2nd part) */
|
||||
temp |= ((cycle & 4) << 2);
|
||||
/* TL indicates current data cycle (0=1st cycle, 1=2nd cycle, etc) */
|
||||
data |= ((xe_1ap[index].Counter & 1) << 4);
|
||||
|
||||
/* TR indicates if data is ready (0=ready, 1=not ready) */
|
||||
/* Fastest One input routine actually expects this bit to switch between 0 & 1 */
|
||||
/* so we make the first read of a data cycle return 1 then 0 for remaining reads */
|
||||
temp |= (!(cycle & 3) << 5);
|
||||
/* TR indicates if data is valid (0=valid, 1=not ready) */
|
||||
/* Some games expect this bit to switch between 0 and 1 */
|
||||
/* so we actually keep it high for some reads after the */
|
||||
/* data cycle has been initialized or incremented */
|
||||
if (xe_1ap[index].Latency)
|
||||
{
|
||||
if (xe_1ap[index].Latency > 1)
|
||||
{
|
||||
/* data is not ready */
|
||||
data |= 0x20;
|
||||
}
|
||||
|
||||
/* Automatically increment data cycle on each read (within current acquisition sequence) */
|
||||
cycle = (cycle + 1) & 7;
|
||||
/* decrement internal latency */
|
||||
xe_1ap[index].Latency--;
|
||||
}
|
||||
else if (xe_1ap[index].Counter <= 10)
|
||||
{
|
||||
/* next data cycle */
|
||||
xe_1ap[index].Counter++;
|
||||
|
||||
/* Update internal cycle counter */
|
||||
xe_1ap[index].Counter = (xe_1ap[index].Counter & ~7) | cycle;
|
||||
/* reinitialize internal latency */
|
||||
xe_1ap[index].Latency = XE_1AP_LATENCY;
|
||||
}
|
||||
|
||||
/* Update internal latency on each read */
|
||||
xe_1ap[index].Latency++;
|
||||
|
||||
return temp;
|
||||
return data;
|
||||
}
|
||||
|
||||
INLINE void xe_1ap_write(int index, unsigned char data, unsigned char mask)
|
||||
{
|
||||
/* update bits set as output only */
|
||||
/* only update bits set as output */
|
||||
data = (xe_1ap[index].State & ~mask) | (data & mask);
|
||||
|
||||
/* look for TH 1->0 transitions */
|
||||
if (!(data & 0x40) && (xe_1ap[index].State & 0x40))
|
||||
{
|
||||
/* reset acquisition cycle */
|
||||
xe_1ap[index].Latency = xe_1ap[index].Counter = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* some games immediately write new data to TH */
|
||||
/* so we make sure first sequence has actually been handled */
|
||||
if (xe_1ap[index].Latency > 2)
|
||||
{
|
||||
/* next acquisition sequence */
|
||||
xe_1ap[index].Counter = (xe_1ap[index].Counter & ~7) + 8;
|
||||
/* reset data acquisition cycle */
|
||||
xe_1ap[index].Counter = 0;
|
||||
|
||||
/* 5 sequence max with 8 cycles each */
|
||||
if (xe_1ap[index].Counter > 32)
|
||||
{
|
||||
xe_1ap[index].Counter = 32;
|
||||
}
|
||||
}
|
||||
/* initialize internal latency */
|
||||
xe_1ap[index].Latency = XE_1AP_LATENCY;
|
||||
}
|
||||
|
||||
/* update internal state */
|
||||
|
@ -2,7 +2,7 @@
|
||||
* Genesis Plus
|
||||
* XE-1AP analog controller support
|
||||
*
|
||||
* Copyright (C) 2011-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 2011-2015 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
@ -4,8 +4,8 @@
|
||||
*
|
||||
* Support for SG-1000 (TMS99xx & 315-5066), Master System (315-5124 & 315-5246), Game Gear & Mega Drive VDP
|
||||
*
|
||||
* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2015 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
@ -360,8 +360,8 @@ void vdp_reset(void)
|
||||
}
|
||||
}
|
||||
|
||||
/* H-INT should be disabled on startup (fixes GG Terminator 2: Judgement Day) */
|
||||
vdp_reg_w(10, 0xFF, 0);
|
||||
/* H-INT is disabled on startup (verified on VA4 MD1 with 315-5313 VDP) */
|
||||
reg[10] = 0xFF;
|
||||
|
||||
/* Master System specific */
|
||||
if ((system_hw & SYSTEM_SMS) && (!(config.bios & 1) || !(system_bios & SYSTEM_SMS)))
|
||||
@ -1396,7 +1396,7 @@ unsigned int vdp_hvc_r(unsigned int cycles)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Mode 4: by default, VCounter runs normally & H counter is frozen */
|
||||
/* Mode 4: by default, VCounter runs normally & HCounter is frozen */
|
||||
data &= 0xff;
|
||||
}
|
||||
}
|
||||
|
@ -4,8 +4,8 @@
|
||||
*
|
||||
* Support for SG-1000 (TMS99xx & 315-5066), Master System (315-5124 & 315-5246), Game Gear & Mega Drive VDP
|
||||
*
|
||||
* Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2014 Eke-Eke (Genesis Plus GX)
|
||||
* Copyright (C) 1998-2003 Charles Mac Donald (original code)
|
||||
* Copyright (C) 2007-2015 Eke-Eke (Genesis Plus GX)
|
||||
*
|
||||
* Redistribution and use of this code or any derivative works are permitted
|
||||
* provided that the following conditions are met:
|
||||
|
Loading…
Reference in New Issue
Block a user