mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-09-10 16:53:15 +02:00
.fixed SUB-CPU access to unmapped areas using PC-relative instructions (Final Fight CD first boss crash)
.fixed SUB-CPU idle loop false detection when using BSET/BCLR on memory mode register (Pugsy CD first boss slowdowns) .fixed Word-RAM default mode switching on soft reset .optimized VDP DMA processing
This commit is contained in:
EkeEke
parent
e53d6e8aa4
commit
2b8656c27f
@ -412,6 +412,7 @@ INLINE void word_ram_switch(uint8 mode)
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if (mode & 0x04)
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{
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/* 2M -> 1M mode */
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for (i=0; i<0x10000; i++)
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{
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*ptr2++=*ptr1++;
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@ -420,11 +421,43 @@ INLINE void word_ram_switch(uint8 mode)
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}
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else
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{
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/* 1M -> 2M mode */
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for (i=0; i<0x10000; i++)
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{
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*ptr1++=*ptr2++;
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*ptr1++=*ptr3++;
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}
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/* allow Word-RAM access from both CPU in 2M mode (fixes sync issues in Mortal Kombat) */
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for (i=scd.cartridge.boot+0x20; i<scd.cartridge.boot+0x24; i++)
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{
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/* MAIN-CPU: $200000-$23FFFF is mapped to 256K Word-RAM */
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m68k.memory_map[i].base = scd.word_ram_2M + ((i & 0x03) << 16);
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m68k.memory_map[i].read8 = NULL;
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m68k.memory_map[i].read16 = NULL;
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m68k.memory_map[i].write8 = NULL;
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m68k.memory_map[i].write16 = NULL;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = NULL;
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}
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for (i=0x08; i<0x0c; i++)
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{
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/* SUB-CPU: $080000-$0BFFFF is mapped to 256K Word-RAM */
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s68k.memory_map[i].read8 = NULL;
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s68k.memory_map[i].read16 = NULL;
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s68k.memory_map[i].write8 = NULL;
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s68k.memory_map[i].write16 = NULL;
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}
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for (i=0x0c; i<0x0e; i++)
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{
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/* SUB-CPU: $0C0000-$0DFFFF is unmapped */
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s68k.memory_map[i].read8 = s68k_read_bus_8;
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s68k.memory_map[i].read16 = s68k_read_bus_16;
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s68k.memory_map[i].write8 = s68k_unused_8_w;
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s68k.memory_map[i].write16 = s68k_unused_16_w;
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}
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}
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}
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@ -471,12 +504,12 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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case 0x03: /* Memory Mode */
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{
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s68k_poll_sync(0x02);
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/* detect MODE & RET bits modifications */
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if ((data ^ scd.regs[0x03 >> 1].byte.l) & 0x05)
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{
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int i;
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s68k_poll_sync(0x02);
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/* MODE bit */
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if (data & 0x04)
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@ -485,7 +518,7 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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if (!(scd.regs[0x03 >> 1].byte.l & 0x04))
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{
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/* re-arrange Word-RAM banks */
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word_ram_switch(data);
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word_ram_switch(0x04);
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}
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/* RET bit in 1M Mode */
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@ -501,7 +534,6 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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for (i=scd.cartridge.boot+0x22; i<scd.cartridge.boot+0x24; i++)
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{
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/* VRAM cell image mapped at $220000-$23FFFF */
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m68k.memory_map[i].base = NULL;
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m68k.memory_map[i].read8 = cell_ram_1_read8;
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m68k.memory_map[i].read16 = cell_ram_1_read16;
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m68k.memory_map[i].write8 = cell_ram_1_write8;
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@ -545,7 +577,6 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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for (i=scd.cartridge.boot+0x22; i<scd.cartridge.boot+0x24; i++)
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{
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/* VRAM cell image mapped at $220000-$23FFFF */
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m68k.memory_map[i].base = NULL;
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m68k.memory_map[i].read8 = cell_ram_0_read8;
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m68k.memory_map[i].read16 = cell_ram_0_read16;
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m68k.memory_map[i].write8 = cell_ram_0_write8;
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@ -585,38 +616,7 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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if (scd.regs[0x02 >> 1].byte.l & 0x04)
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{
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/* re-arrange Word-RAM banks */
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word_ram_switch(data);
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/* allow Word-RAM access from both CPU in 2M mode (fixes sync issues in Mortal Kombat) */
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for (i=scd.cartridge.boot+0x20; i<scd.cartridge.boot+0x24; i++)
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{
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/* MAIN-CPU: $200000-$23FFFF is mapped to 256K Word-RAM */
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m68k.memory_map[i].base = scd.word_ram_2M + ((i & 0x03) << 16);
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m68k.memory_map[i].read8 = NULL;
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m68k.memory_map[i].read16 = NULL;
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m68k.memory_map[i].write8 = NULL;
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m68k.memory_map[i].write16 = NULL;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = NULL;
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}
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for (i=0x08; i<0x0c; i++)
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{
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/* SUB-CPU: $080000-$0BFFFF is mapped to 256K Word-RAM */
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s68k.memory_map[i].read8 = NULL;
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s68k.memory_map[i].read16 = NULL;
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s68k.memory_map[i].write8 = NULL;
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s68k.memory_map[i].write16 = NULL;
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}
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for (i=0x0c; i<0x0e; i++)
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{
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/* SUB-CPU: $0C0000-$0DFFFF is unmapped */
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s68k.memory_map[i].read8 = s68k_read_bus_8;
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s68k.memory_map[i].read16 = s68k_read_bus_16;
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s68k.memory_map[i].write8 = s68k_unused_8_w;
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s68k.memory_map[i].write16 = s68k_unused_16_w;
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}
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word_ram_switch(0x00);
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/* RET bit set during 1M mode ? */
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data |= ~scd.dmna & 0x01;
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@ -777,12 +777,12 @@ static void scd_write_word(unsigned int address, unsigned int data)
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case 0x02: /* Memory Mode */
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{
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s68k_poll_sync(0x02);
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/* detect MODE & RET bits modifications */
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if ((data ^ scd.regs[0x03>>1].byte.l) & 0x05)
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{
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int i;
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s68k_poll_sync(0x02);
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/* MODE bit */
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if (data & 0x04)
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@ -791,7 +791,7 @@ static void scd_write_word(unsigned int address, unsigned int data)
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if (!(scd.regs[0x03 >> 1].byte.l & 0x04))
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{
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/* re-arrange Word-RAM banks */
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word_ram_switch(data);
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word_ram_switch(0x04);
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}
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/* RET bit in 1M Mode */
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@ -807,7 +807,6 @@ static void scd_write_word(unsigned int address, unsigned int data)
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for (i=scd.cartridge.boot+0x22; i<scd.cartridge.boot+0x24; i++)
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{
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/* VRAM cell image mapped at $220000-$23FFFF */
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m68k.memory_map[i].base = NULL;
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m68k.memory_map[i].read8 = cell_ram_1_read8;
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m68k.memory_map[i].read16 = cell_ram_1_read16;
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m68k.memory_map[i].write8 = cell_ram_1_write8;
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@ -851,7 +850,6 @@ static void scd_write_word(unsigned int address, unsigned int data)
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for (i=scd.cartridge.boot+0x22; i<scd.cartridge.boot+0x24; i++)
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{
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/* VRAM cell image mapped at $220000-$23FFFF */
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m68k.memory_map[i].base = NULL;
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m68k.memory_map[i].read8 = cell_ram_0_read8;
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m68k.memory_map[i].read16 = cell_ram_0_read16;
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m68k.memory_map[i].write8 = cell_ram_0_write8;
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@ -891,38 +889,7 @@ static void scd_write_word(unsigned int address, unsigned int data)
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if (scd.regs[0x03>>1].byte.l & 0x04)
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{
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/* re-arrange Word-RAM banks */
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word_ram_switch(data);
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/* allow Word-RAM access from both CPU in 2M mode (fixes sync issues in Mortal Kombat) */
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for (i=scd.cartridge.boot+0x20; i<scd.cartridge.boot+0x24; i++)
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{
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/* MAIN-CPU: $200000-$23FFFF is mapped to 256K Word-RAM */
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m68k.memory_map[i].base = scd.word_ram_2M + ((i & 0x03) << 16);
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m68k.memory_map[i].read8 = NULL;
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m68k.memory_map[i].read16 = NULL;
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m68k.memory_map[i].write8 = NULL;
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m68k.memory_map[i].write16 = NULL;
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zbank_memory_map[i].read = NULL;
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zbank_memory_map[i].write = NULL;
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}
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for (i=0x08; i<0x0c; i++)
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{
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/* SUB-CPU: $080000-$0BFFFF is mapped to 256K Word-RAM */
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s68k.memory_map[i].read8 = NULL;
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s68k.memory_map[i].read16 = NULL;
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s68k.memory_map[i].write8 = NULL;
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s68k.memory_map[i].write16 = NULL;
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}
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for (i=0x0c; i<0x0e; i++)
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{
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/* SUB-CPU: $0C0000-$0DFFFF is unmapped */
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s68k.memory_map[i].read8 = s68k_read_bus_8;
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s68k.memory_map[i].read16 = s68k_read_bus_16;
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s68k.memory_map[i].write8 = s68k_unused_8_w;
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s68k.memory_map[i].write16 = s68k_unused_16_w;
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}
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word_ram_switch(0x00);
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/* RET bit set during 1M mode ? */
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data |= ~scd.dmna & 0x01;
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@ -1104,7 +1071,7 @@ void scd_init(void)
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/* $240000-$3FFFFF (resp. $400000-$7FFFFF): unused area (Word-RAM mirrored ?) */
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for (i=base+0x24; i<base+0x40; i++)
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{
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m68k.memory_map[i].base = NULL;
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m68k.memory_map[i].base = scd.word_ram_2M + ((i & 3) << 16);
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m68k.memory_map[i].read8 = m68k_read_bus_8;
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m68k.memory_map[i].read16 = m68k_read_bus_16;
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m68k.memory_map[i].write8 = m68k_unused_8_w;
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@ -1143,10 +1110,10 @@ void scd_init(void)
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s68k.memory_map[i].write16 = NULL;
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}
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/* $0C0000-$FD0000: Unused area */
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/* $0C0000-$FD0000: Unused area (Word-RAM mirrored ?) */
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for (i=0x0c; i<0xfd; i++)
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{
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s68k.memory_map[i].base = NULL;
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s68k.memory_map[i].base = scd.word_ram_2M + ((i & 3) << 16);
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s68k.memory_map[i].read8 = s68k_read_bus_8;
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s68k.memory_map[i].read16 = s68k_read_bus_16;
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s68k.memory_map[i].write8 = s68k_unused_8_w;
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@ -1205,6 +1172,9 @@ void scd_reset(int hard)
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/* Power ON initial values (MAIN-CPU side) */
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scd.regs[0x00>>1].w = 0x0002;
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scd.regs[0x02>>1].w = 0x0001;
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/* 2M mode */
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word_ram_switch(0);
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}
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else
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{
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@ -96,6 +96,27 @@ void (*vdp_z80_data_w)(unsigned int data);
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unsigned int (*vdp_68k_data_r)(void);
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unsigned int (*vdp_z80_data_r)(void);
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/* Function prototypes */
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static void vdp_68k_data_w_m4(unsigned int data);
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static void vdp_68k_data_w_m5(unsigned int data);
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static unsigned int vdp_68k_data_r_m4(void);
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static unsigned int vdp_68k_data_r_m5(void);
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static void vdp_z80_data_w_m4(unsigned int data);
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static void vdp_z80_data_w_m5(unsigned int data);
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static unsigned int vdp_z80_data_r_m4(void);
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static unsigned int vdp_z80_data_r_m5(void);
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static void vdp_z80_data_w_ms(unsigned int data);
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static void vdp_z80_data_w_gg(unsigned int data);
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static void vdp_z80_data_w_sg(unsigned int data);
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static void vdp_bus_w(unsigned int data);
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static void vdp_fifo_update(unsigned int cycles);
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static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles);
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static void vdp_dma_68k_ext(unsigned int length);
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static void vdp_dma_68k_ram(unsigned int length);
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static void vdp_dma_68k_io(unsigned int length);
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static void vdp_dma_copy(unsigned int length);
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static void vdp_dma_fill(unsigned int length);
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/* Tables that define the playfield layout */
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static const uint8 hscroll_mask_table[] = { 0x00, 0x07, 0xF8, 0xFF };
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static const uint8 shift_table[] = { 6, 7, 0, 8 };
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@ -121,14 +142,6 @@ static uint16 fifo[4]; /* FIFO buffer */
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static void (*set_irq_line)(unsigned int level);
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static void (*set_irq_line_delay)(unsigned int level);
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/* DMA Timings */
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static const uint8 dma_timing[2][2] =
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{
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/* H32, H40 */
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{16 , 18}, /* active display */
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{167, 205} /* blank display */
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};
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/* Vertical counter overflow values (see hvc.h) */
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static const uint16 vc_table[4][2] =
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{
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@ -139,27 +152,30 @@ static const uint16 vc_table[4][2] =
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{0x106, 0x10A} /* Mode 5 (240 lines) */
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};
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/*--------------------------------------------------------------------------*/
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/* Function prototypes */
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/*--------------------------------------------------------------------------*/
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/* DMA Timings (number of access slots per line) */
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static const uint8 dma_timing[2][2] =
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{
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/* H32, H40 */
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{16 , 18}, /* active display */
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{167, 205} /* blank display */
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};
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/* DMA processing functions (set by VDP register 23 high nibble) */
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static void (*const dma_func[16])(unsigned int length) =
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{
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/* 0x0-0x3 : DMA from 68k bus $000000-$7FFFFF (external area) */
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vdp_dma_68k_ext,vdp_dma_68k_ext,vdp_dma_68k_ext,vdp_dma_68k_ext,
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/* 0x4-0x7 : DMA from 68k bus $800000-$FFFFFF (internal RAM & I/O) */
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vdp_dma_68k_ram, vdp_dma_68k_io,vdp_dma_68k_ram,vdp_dma_68k_ram,
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/* 0x8-0xB : DMA Fill */
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vdp_dma_fill,vdp_dma_fill,vdp_dma_fill,vdp_dma_fill,
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/* 0xC-0xF : DMA Copy */
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vdp_dma_copy,vdp_dma_copy,vdp_dma_copy,vdp_dma_copy
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};
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static void vdp_68k_data_w_m4(unsigned int data);
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static void vdp_68k_data_w_m5(unsigned int data);
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static unsigned int vdp_68k_data_r_m4(void);
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static unsigned int vdp_68k_data_r_m5(void);
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static void vdp_z80_data_w_m4(unsigned int data);
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static void vdp_z80_data_w_m5(unsigned int data);
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static unsigned int vdp_z80_data_r_m4(void);
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static unsigned int vdp_z80_data_r_m5(void);
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static void vdp_z80_data_w_ms(unsigned int data);
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static void vdp_z80_data_w_gg(unsigned int data);
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static void vdp_z80_data_w_sg(unsigned int data);
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static void vdp_bus_w(unsigned int data);
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static void vdp_fifo_update(unsigned int cycles);
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static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles);
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static void vdp_dma_copy(unsigned int length);
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static void vdp_dma_vbus(unsigned int length);
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static void vdp_dma_fill(unsigned char data, unsigned int length);
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/*--------------------------------------------------------------------------*/
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/* Init, reset, context functions */
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@ -608,30 +624,8 @@ void vdp_dma_update(unsigned int cycles)
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/* Update DMA length */
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dma_length -= dma_bytes;
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/* Select DMA operation */
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switch (dma_type)
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{
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case 2:
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{
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/* VRAM Fill */
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vdp_dma_fill(dmafill, dma_bytes);
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break;
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}
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case 3:
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{
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/* VRAM Copy */
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vdp_dma_copy(dma_bytes);
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break;
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}
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default:
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{
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/* 68K bus to VRAM, CRAM or VSRAM */
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vdp_dma_vbus(dma_bytes);
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break;
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}
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}
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/* Process DMA operation */
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dma_func[reg[23] >> 4](dma_bytes);
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/* Check if DMA is finished */
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if (!dma_length)
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@ -2868,78 +2862,112 @@ static void vdp_z80_data_w_sg(unsigned int data)
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/* DMA operations */
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/*--------------------------------------------------------------------------*/
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/* 68K bus to VRAM, VSRAM or CRAM */
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static void vdp_dma_vbus(unsigned int length)
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/* DMA from 68K bus: $000000-$7FFFFF (external area) */
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static void vdp_dma_68k_ext(unsigned int length)
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{
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uint16 data;
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/* 68k bus source address */
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uint32 source = (reg[23] << 17) | (dma_src << 1);
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|
||||
/* Z80 & I/O area ($A00000-$A1FFFF) specific */
|
||||
if (reg[23] == 0x50)
|
||||
do
|
||||
{
|
||||
do
|
||||
/* Read data word from 68k bus */
|
||||
if (m68k.memory_map[source>>16].read16)
|
||||
{
|
||||
/* Z80 area */
|
||||
if (source <= 0xA0FFFF)
|
||||
{
|
||||
/* Return $FFFF only when the Z80 isn't hogging the Z-bus.
|
||||
(e.g. Z80 isn't reset and 68000 has the bus) */
|
||||
data = ((zstate ^ 3) ? *(uint16 *)(work_ram + (source & 0xFFFF)) : 0xFFFF);
|
||||
}
|
||||
|
||||
/* The I/O chip and work RAM try to drive the data bus which results
|
||||
in both values being combined in random ways when read.
|
||||
We return the I/O chip values which seem to have precedence, */
|
||||
else if (source <= 0xA1001F)
|
||||
{
|
||||
data = io_68k_read((source >> 1) & 0x0F);
|
||||
data = (data << 8 | data);
|
||||
}
|
||||
|
||||
/* All remaining locations access work RAM */
|
||||
else
|
||||
{
|
||||
data = *(uint16 *)(work_ram + (source & 0xFFFF));
|
||||
}
|
||||
|
||||
/* Increment source address */
|
||||
source += 2;
|
||||
|
||||
/* 128k DMA window */
|
||||
source = (reg[23] << 17) | (source & 0x1FFFF);
|
||||
|
||||
/* Write data to VRAM, CRAM or VSRAM */
|
||||
vdp_bus_w(data);
|
||||
data = m68k.memory_map[source>>16].read16(source);
|
||||
}
|
||||
while (--length);
|
||||
}
|
||||
else
|
||||
{
|
||||
do
|
||||
else
|
||||
{
|
||||
/* Read data word from 68k bus */
|
||||
if (m68k.memory_map[source>>16].base)
|
||||
{
|
||||
data = *(uint16 *)(m68k.memory_map[source>>16].base + (source & 0xFFFF));
|
||||
}
|
||||
else
|
||||
{
|
||||
data = m68k.memory_map[source>>16].read16(source);
|
||||
}
|
||||
data = *(uint16 *)(m68k.memory_map[source>>16].base + (source & 0xFFFF));
|
||||
}
|
||||
|
||||
/* Increment source address */
|
||||
source += 2;
|
||||
/* Increment source address */
|
||||
source += 2;
|
||||
|
||||
/* 128k DMA window */
|
||||
source = (reg[23] << 17) | (source & 0x1FFFF);
|
||||
/* 128k DMA window */
|
||||
source = (reg[23] << 17) | (source & 0x1FFFF);
|
||||
|
||||
/* Write data word to VRAM, CRAM or VSRAM */
|
||||
vdp_bus_w(data);
|
||||
}
|
||||
while (--length);
|
||||
/* Write data word to VRAM, CRAM or VSRAM */
|
||||
vdp_bus_w(data);
|
||||
}
|
||||
while (--length);
|
||||
|
||||
/* Update DMA source address */
|
||||
dma_src = (source >> 1) & 0xffff;
|
||||
}
|
||||
|
||||
/* DMA from 68K bus: $800000-$FFFFFF (internal area) except I/O area */
|
||||
static void vdp_dma_68k_ram(unsigned int length)
|
||||
{
|
||||
uint16 data;
|
||||
|
||||
/* 68k bus source address */
|
||||
uint32 source = (reg[23] << 17) | (dma_src << 1);
|
||||
|
||||
do
|
||||
{
|
||||
/* access Work-RAM by default */
|
||||
data = *(uint16 *)(work_ram + (source & 0xFFFF));
|
||||
|
||||
/* Increment source address */
|
||||
source += 2;
|
||||
|
||||
/* 128k DMA window */
|
||||
source = (reg[23] << 17) | (source & 0x1FFFF);
|
||||
|
||||
/* Write data word to VRAM, CRAM or VSRAM */
|
||||
vdp_bus_w(data);
|
||||
}
|
||||
while (--length);
|
||||
|
||||
/* Update DMA source address */
|
||||
dma_src = (source >> 1) & 0xffff;
|
||||
}
|
||||
|
||||
/* DMA from 68K bus: $A00000-$A1FFFF (I/O area) specific */
|
||||
static void vdp_dma_68k_io(unsigned int length)
|
||||
{
|
||||
uint16 data;
|
||||
|
||||
/* 68k bus source address */
|
||||
uint32 source = (reg[23] << 17) | (dma_src << 1);
|
||||
|
||||
do
|
||||
{
|
||||
/* Z80 area */
|
||||
if (source <= 0xA0FFFF)
|
||||
{
|
||||
/* Return $FFFF only when the Z80 isn't hogging the Z-bus.
|
||||
(e.g. Z80 isn't reset and 68000 has the bus) */
|
||||
data = ((zstate ^ 3) ? *(uint16 *)(work_ram + (source & 0xFFFF)) : 0xFFFF);
|
||||
}
|
||||
|
||||
/* The I/O chip and work RAM try to drive the data bus which results
|
||||
in both values being combined in random ways when read.
|
||||
We return the I/O chip values which seem to have precedence, */
|
||||
else if (source <= 0xA1001F)
|
||||
{
|
||||
data = io_68k_read((source >> 1) & 0x0F);
|
||||
data = (data << 8 | data);
|
||||
}
|
||||
|
||||
/* All remaining locations access work RAM */
|
||||
else
|
||||
{
|
||||
data = *(uint16 *)(work_ram + (source & 0xFFFF));
|
||||
}
|
||||
|
||||
/* Increment source address */
|
||||
source += 2;
|
||||
|
||||
/* 128k DMA window */
|
||||
source = (reg[23] << 17) | (source & 0x1FFFF);
|
||||
|
||||
/* Write data to VRAM, CRAM or VSRAM */
|
||||
vdp_bus_w(data);
|
||||
}
|
||||
while (--length);
|
||||
|
||||
/* Update DMA source address */
|
||||
dma_src = (source >> 1) & 0xffff;
|
||||
@ -2989,12 +3017,14 @@ static void vdp_dma_copy(unsigned int length)
|
||||
}
|
||||
|
||||
/* VRAM Fill (TODO: check if CRAM or VSRAM fill is possible) */
|
||||
static void vdp_dma_fill(unsigned char data, unsigned int length)
|
||||
static void vdp_dma_fill(unsigned int length)
|
||||
{
|
||||
/* VRAM write operation only (Williams Greatest Hits after soft reset) */
|
||||
if ((code & 0x1F) == 0x01)
|
||||
{
|
||||
int name;
|
||||
uint8 data = dmafill;
|
||||
|
||||
do
|
||||
{
|
||||
/* Intercept writes to Sprite Attribute Table */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user