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https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-04 18:05:06 +01:00
[SCD] implemented cycle-accurate stopwatch counter
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EkeEke
parent
b28c86d826
commit
46e1894d7a
@ -285,7 +285,7 @@ static unsigned int scd_read_byte(unsigned int address)
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if (address == 0xff8000)
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{
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/* register $00 is reserved for MAIN-CPU, we use $06 instead */
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return scd.regs[0x06 >> 1].byte.h;
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return scd.regs[0x06>>1].byte.h;
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}
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/* RESET status */
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@ -299,10 +299,10 @@ static unsigned int scd_read_byte(unsigned int address)
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if ((address >= 0xff8050) && (address <= 0xff8056))
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{
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/* shifted 4-bit input (xxxx00) */
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uint8 bits = (scd.regs[0x4e >> 1].w >> (((address & 6) ^ 6) << 1)) << 2;
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uint8 bits = (scd.regs[0x4e>>1].w >> (((address & 6) ^ 6) << 1)) << 2;
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/* color code */
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uint8 code = scd.regs[0x4c >> 1].byte.l;
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uint8 code = scd.regs[0x4c>>1].byte.l;
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/* 16-bit font data (4 pixels = 16 bits) */
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uint16 data = (code >> (bits & 4)) & 0x0f;
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@ -320,7 +320,7 @@ static unsigned int scd_read_byte(unsigned int address)
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}
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/* MAIN-CPU communication words */
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if ((address & 0xf0) == 0x10)
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if ((address & 0x1f0) == 0x10)
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{
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s68k_poll_detect(address & 0x1f);
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}
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@ -366,17 +366,24 @@ static unsigned int scd_read_word(unsigned int address)
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if (address == 0xff8000)
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{
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/* register $00 is reserved for MAIN-CPU, we use $06 instead */
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return scd.regs[0x06 >> 1].w;
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return scd.regs[0x06>>1].w;
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}
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/* Stopwatch counter (word access only ?) */
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if (address == 0xff800c)
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{
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/* cycle-accurate counter value */
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return (scd.regs[0x0c>>1].w + ((s68k.cycles - scd.stopwatch) / TIMERS_SCYCLES_RATIO)) & 0xfff;
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}
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/* Font data */
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if ((address >= 0xff8050) && (address <= 0xff8056))
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{
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/* shifted 4-bit input (xxxx00) */
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uint8 bits = (scd.regs[0x4e >> 1].w >> (((address & 6) ^ 6) << 1)) << 2;
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uint8 bits = (scd.regs[0x4e>>1].w >> (((address & 6) ^ 6) << 1)) << 2;
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/* color code */
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uint8 code = scd.regs[0x4c >> 1].byte.l;
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uint8 code = scd.regs[0x4c>>1].byte.l;
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/* 16-bit font data (4 pixels = 16 bits) */
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uint16 data = (code >> (bits & 4)) & 0x0f;
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@ -394,7 +401,7 @@ static unsigned int scd_read_word(unsigned int address)
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}
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/* MAIN-CPU communication words */
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if ((address & 0xf0) == 0x10)
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if ((address & 0x1f0) == 0x10)
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{
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/* relative MAIN-CPU cycle counter */
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unsigned int cycles = (s68k.cycles * MCYCLES_PER_LINE) / SCYCLES_PER_LINE;
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@ -682,7 +689,7 @@ static void scd_write_byte(unsigned int address, unsigned int data)
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case 0x31: /* Timer */
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{
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/* reload timer (one timer clock = 384 CPU cycles) */
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scd.timer = data * 384 * 4;
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scd.timer = data * TIMERS_SCYCLES_RATIO;
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/* only non-zero data starts timer, writing zero stops it */
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if (data)
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@ -939,8 +946,12 @@ static void scd_write_word(unsigned int address, unsigned int data)
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return;
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}
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case 0x0c: /* Stopwatch */
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case 0x0c: /* Stopwatch (word access only) */
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{
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/* synchronize the counter with SUB-CPU */
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int ticks = (s68k.cycles - scd.stopwatch) / TIMERS_SCYCLES_RATIO;
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scd.stopwatch += (ticks * TIMERS_SCYCLES_RATIO);
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/* any writes clear the counter */
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scd.regs[0x0c>>1].w = 0;
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return;
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@ -961,7 +972,7 @@ static void scd_write_word(unsigned int address, unsigned int data)
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data &= 0xff;
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/* reload timer (one timer clock = 384 CPU cycles) */
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scd.timer = data * 384 * 4;
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scd.timer = data * TIMERS_SCYCLES_RATIO;
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/* only non-zero data starts timer, writing zero stops it */
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if (data)
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@ -1187,8 +1198,9 @@ void scd_reset(int hard)
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/* RESET register always return 1 (register $06 is unused by both sides, it is used for SUB-CPU first register) */
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scd.regs[0x06>>1].byte.l = 0x01;
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/* Reset TIMER counter */
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/* Reset TIMER & STOPWATCH counters */
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scd.timer = 0;
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scd.stopwatch = 0;
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/* Reset frame cycle counter */
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scd.cycles = 0;
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@ -1254,9 +1266,6 @@ void scd_update(unsigned int cycles)
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}
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}
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/* Stop Watch (TODO: improve timing accuracy, one unit = 384 CPU cycles) */
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scd.regs[0x0c>>1].w = (scd.regs[0x0c>>1].w + 2) & 0xfff;
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/* Timer */
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if (scd.timer)
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{
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@ -1265,7 +1274,7 @@ void scd_update(unsigned int cycles)
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if (scd.timer <= 0)
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{
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/* reload timer (one timer clock = 384 CPU cycles) */
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scd.timer += (scd.regs[0x30>>1].byte.l * 384 * 4);
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scd.timer += (scd.regs[0x30>>1].byte.l * TIMERS_SCYCLES_RATIO);
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/* level 3 interrupt enabled ? */
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if (scd.regs[0x32>>1].byte.l & 0x08)
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@ -1287,6 +1296,24 @@ void scd_update(unsigned int cycles)
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}
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}
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void scd_end_frame(unsigned int cycles)
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{
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/* run Stopwatch until end of frame */
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int ticks = (cycles - scd.stopwatch) / TIMERS_SCYCLES_RATIO;
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scd.regs[0x0c>>1].w = (scd.regs[0x0c>>1].w + ticks) & 0xfff;
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/* adjust Stopwatch counter for next frame (can be negative) */
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scd.stopwatch += (ticks * TIMERS_SCYCLES_RATIO) - cycles;
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/* adjust SUB-CPU & GPU cycle counters for next frame */
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s68k.cycles -= cycles;
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gfx.cycles -= cycles;
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/* reset CPU registers polling */
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m68k.poll.cycle = 0;
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s68k.poll.cycle = 0;
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}
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int scd_context_save(uint8 *state)
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{
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uint16 tmp16;
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@ -46,11 +46,15 @@
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#define scd ext.cd_hw
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/* 5000000 clocks/s = approx. 3184 clocks/line with a master clock of 53.693175 Mhz */
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/* TODO: use emulated master clock as reference ? */
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/* 5000000 SCD clocks/s = ~3184 clocks/line with a Master Clock of 53.693175 MHz */
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/* This would be slightly (~30 clocks) more on PAL systems because of the slower */
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/* Master Clock (53.203424 MHz) but not enough to really care about since clocks */
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/* are not running in sync anyway. */
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#define SCD_CLOCK 50000000
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#define SCYCLES_PER_LINE 3184
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/* Timer & Stopwatch clocks divider */
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#define TIMERS_SCYCLES_RATIO (384 * 4)
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/* CD hardware */
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typedef struct
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@ -63,6 +67,7 @@ typedef struct
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uint8 bram[0x2000]; /* 8K Backup RAM */
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reg16_t regs[0x100]; /* 256 x 16-bit ASIC registers */
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uint32 cycles; /* Master clock counter */
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int32 stopwatch; /* Clockwatch counter */
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int32 timer; /* Timer counter */
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uint8 pending; /* Pending interrupts */
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uint8 dmna; /* Pending DMNA write status */
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@ -76,6 +81,7 @@ typedef struct
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extern void scd_init(void);
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extern void scd_reset(int hard);
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extern void scd_update(unsigned int cycles);
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extern void scd_end_frame(unsigned int cycles);
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extern int scd_context_load(uint8 *state);
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extern int scd_context_save(uint8 *state);
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extern int scd_68k_irq_ack(int level);
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@ -466,6 +466,16 @@ unsigned int ctrl_io_read_word(unsigned int address)
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return *(uint16 *)(m68k.memory_map[0].base + 0x72);
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}
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/* Stopwatch counter (word read access only ?) */
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if (index == 0x0c)
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{
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/* relative SUB-CPU cycle counter */
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unsigned int cycles = (m68k.cycles * SCYCLES_PER_LINE) / MCYCLES_PER_LINE;
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/* cycle-accurate counter value */
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return (scd.regs[0x0c>>1].w + ((cycles - scd.stopwatch) / TIMERS_SCYCLES_RATIO)) & 0xfff;
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}
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/* default registers */
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if (index < 0x30)
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{
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@ -992,15 +992,12 @@ void system_frame_scd(int do_skip)
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}
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while (++line < (lines_per_frame - 1));
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/* reset CPU registers polling */
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m68k.poll.cycle = 0;
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s68k.poll.cycle = 0;
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/* prepare for next SCD frame */
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scd_end_frame(scd.cycles);
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/* adjust CPU cycle counters for next frame */
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Z80.cycles -= mcycles_vdp;
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m68k.cycles -= mcycles_vdp;
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s68k.cycles -= scd.cycles;
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gfx.cycles -= scd.cycles;
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}
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void system_frame_sms(int do_skip)
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