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[Core/MCD] fixed PRG-RAM access from MAIN-CPU side on system reset
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parent
72ddc6e985
commit
4a41e0cca7
@ -1519,6 +1519,20 @@ void scd_reset(int hard)
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m68k.memory_map[scd.cartridge.boot + 0x02].base = scd.prg_ram;
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m68k.memory_map[scd.cartridge.boot + 0x03].base = scd.prg_ram + 0x10000;
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/* allow access to PRG-RAM from MAIN-CPU */
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m68k.memory_map[scd.cartridge.boot + 0x02].read8 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x03].read8 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x02].read16 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x03].read16 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x02].write8 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x03].write8 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x02].write16 = NULL;
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m68k.memory_map[scd.cartridge.boot + 0x03].write16 = NULL;
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zbank_memory_map[scd.cartridge.boot + 0x02].read = NULL;
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zbank_memory_map[scd.cartridge.boot + 0x03].read = NULL;
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zbank_memory_map[scd.cartridge.boot + 0x02].write = NULL;
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zbank_memory_map[scd.cartridge.boot + 0x03].write = NULL;
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/* reset & halt SUB-CPU */
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s68k.cycles = 0;
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s68k_pulse_reset();
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@ -331,7 +331,7 @@ void z80_gg_port_w(unsigned int port, unsigned char data)
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}
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}
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/* full address range is decoded by Game Gear I/O chip (fixes G-Loc) */
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/* full address range is decoded by Game Gear I/O chip (fixes G-LOC Air Battle) */
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else if ((port == 0x3E) || (port == 0x3F))
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{
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io_z80_write(port & 1, data, Z80.cycles + SMS_CYCLE_OFFSET);
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