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[Core/Sound] fixed MAME YM2413 core EG updates being 2x faster after EG resolution change and improved EG increment steps accuracy (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-03-20)
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ekeeke
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14
HISTORY.txt
14
HISTORY.txt
@ -139,24 +139,20 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
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[Core/Sound]
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---------------
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* replaced configurable YM2612 DAC quantization by configurable YM2612 chip model emulation (discrete, ASIC-integrated or enhanced)
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* added DAC distortion emulation for discrete YM2612 chip model
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* added accurate status & BUSY flag emulation for discrete and ASIC-integrated YM2612 chip models (verified on real hardware)
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* added optional support for cycle-accurate YM3438/YM2612 & YM2413 cores from Nuked
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* improved 9-bit DAC quantization accuracy for discrete and ASIC-integrated YM2612 chip models (verified on YM2612 die)
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* rewrote optimized & more accurate PSG core from scratch
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* removed PSG boost noise feature & added optional high-quality PSG resampling
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* rewrote optimized & more accurate PSG core from scratch
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* replaced configurable YM2612 DAC quantization by configurable YM2612 chip model emulation (discrete, ASIC-integrated or enhanced)
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* improved 9-bit DAC quantization accuracy for discrete and ASIC-integrated YM2612 chip models (verified on YM2612 die)
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* improved YM2413 EG accuracy (verified on YM2413 real hardware)
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* fixed YM2612 self-feedback regression introduced in 1.7.1
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* fixed YM2612 one-sample extra delay on operator1 output
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* fixed YM2612 LFO PM implementation: block & keyscale code should not be modified by LFO (verified on YM2612 die)
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* fixed YM2612 Timer B overflow handling
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* fixed YM2413 carrier/modulator phase reset after channel Key ON (Japanese Master System BIOS music)
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* fixed YM2413 carrier/modulator phase reset after channel Key ON (fixes Japanese Master System BIOS music)
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* fixed YM2413 intruments ROM (verified on YM2413B die)
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* fixed YM2413 EG resolution bits (verified on YM2413B die)
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* fixed YM2413 EG dump rate (verified on YM2413 hardware)
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* fixed YM2413 EG behavior for fastest attack rates (verified on YM2413 hardware)
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* fixed YM2413 EG behavior when SL=0 (verified on YM2413 hardware)
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* improved YM2413 EG sustain phase transition comparator accuracy (verified on YM2413 real hardware)
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[Gamecube/Wii]
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---------------
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@ -36,6 +36,8 @@ to do:
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/** 2021/04/25: fixed EG behavior for fastest attack rates (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2017-01-26) **/
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/** 2021/04/25: fixed EG behavior when SL = 0 (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-12-24) **/
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/** 2021/04/25: improved EG sustain phase transition comparator accuracy (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-12-31) **/
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/** 2021/05/04: improved EG increment steps accuracy (verified on YM2413 real hardware, cf. https://www.smspower.org/Development/YM2413ReverseEngineeringNotes2015-03-20) **/
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/************************************************/
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#include "shared.h"
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@ -229,29 +231,29 @@ static const UINT32 sl_tab[16]={
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#undef SC
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#define RATE_STEPS (8)
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#define RATE_STEPS (16)
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static const unsigned char eg_inc[15*RATE_STEPS]={
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/*cycle:0 1 2 3 4 5 6 7*/
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/*cycle:0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15*/
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/* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
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/* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
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/* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
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/* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
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/* 0 */ 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
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/* 1 */ 0,1, 0,1, 1,1, 0,1, 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
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/* 2 */ 0,1, 1,1, 0,1, 1,1, 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
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/* 3 */ 0,1, 1,1, 1,1, 1,1, 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
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/* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
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/* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
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/* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
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/* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
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/* 4 */ 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, 0,1, /* rate 13 0 (increment by 0 or 1) */
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/* 5 */ 0,1, 0,1, 1,1, 1,1, 0,1, 0,1, 0,1, 0,1, /* rate 13 1 */
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/* 6 */ 0,1, 0,1, 1,1, 1,1, 0,1, 0,1, 1,1, 1,1, /* rate 13 2 */
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/* 7 */ 0,1, 0,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, /* rate 13 3 */
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/* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
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/* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
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/*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
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/*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
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/* 8 */ 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, 1,1, /* rate 14 0 (increment by 1) */
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/* 9 */ 1,1, 1,1, 2,2, 2,2, 1,1, 1,1, 1,1, 1,1, /* rate 14 1 */
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/*10 */ 1,1, 1,1, 2,2, 2,2, 1,1, 1,1, 2,2, 2,2, /* rate 14 2 */
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/*11 */ 1,1, 1,1, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, /* rate 14 3 */
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/*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay (increment by 4) */
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/*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (not used as attack phase is skipped in these cases) */
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/*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
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/*12 */ 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, 2,2, /* rates 15 0, 15 1, 15 2, 15 3 for decay (increment by 2) */
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/*13 */ 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for attack (not used as attack phase is skipped in these cases) */
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/*14 */ 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
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};
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@ -581,7 +583,7 @@ INLINE void advance(void)
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case EG_DMP: /* dump phase */
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_dp)-1) ) )
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{
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op->volume += eg_inc[op->eg_sel_dp + ((ym2413.eg_cnt>>op->eg_sh_dp)&7)];
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op->volume += eg_inc[op->eg_sel_dp + ((ym2413.eg_cnt>>op->eg_sh_dp)&15)];
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}
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/* attack phase should be started if attenuation is already maximal, without waiting for next envelope update (every 2 samples during dump phase) */
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@ -613,7 +615,7 @@ INLINE void advance(void)
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
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{
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op->volume += (~op->volume *
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(eg_inc[op->eg_sel_ar + ((ym2413.eg_cnt>>op->eg_sh_ar)&7)])
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(eg_inc[op->eg_sel_ar + ((ym2413.eg_cnt>>op->eg_sh_ar)&15)])
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) >>2;
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if (op->volume <= MIN_ATT_INDEX)
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@ -627,7 +629,7 @@ INLINE void advance(void)
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case EG_DEC: /* decay phase */
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
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{
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op->volume += eg_inc[op->eg_sel_dr + ((ym2413.eg_cnt>>op->eg_sh_dr)&7)];
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op->volume += eg_inc[op->eg_sel_dr + ((ym2413.eg_cnt>>op->eg_sh_dr)&15)];
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if ( (op->volume & ~7) == op->sl ) /* envelope level lowest 3 bits are ignored by the comparator */
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op->state = EG_SUS;
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@ -648,7 +650,7 @@ INLINE void advance(void)
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/* during sustain phase chip adds Release Rate (in percussive mode) */
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
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{
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op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&7)];
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op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&15)];
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if ( op->volume >= MAX_ATT_INDEX )
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op->volume = MAX_ATT_INDEX;
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@ -685,7 +687,7 @@ INLINE void advance(void)
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{
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rs)-1) ) )
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{
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op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&7)];
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op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&15)];
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if ( op->volume >= MAX_ATT_INDEX )
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{
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op->volume = MAX_ATT_INDEX;
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@ -697,7 +699,7 @@ INLINE void advance(void)
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{
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
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{
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op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&7)];
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op->volume += eg_inc[op->eg_sel_rr + ((ym2413.eg_cnt>>op->eg_sh_rr)&15)];
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if ( op->volume >= MAX_ATT_INDEX )
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{
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op->volume = MAX_ATT_INDEX;
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@ -710,7 +712,7 @@ INLINE void advance(void)
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{
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if ( !(ym2413.eg_cnt & ((1<<op->eg_sh_rs)-1) ) )
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{
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op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&7)];
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op->volume += eg_inc[op->eg_sel_rs + ((ym2413.eg_cnt>>op->eg_sh_rs)&15)];
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if ( op->volume >= MAX_ATT_INDEX )
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{
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op->volume = MAX_ATT_INDEX;
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