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https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-09-11 01:03:15 +02:00
[Genesis/VDP] Fixed FIFO access timings when using invalid write code value (fixes Clue menu)
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@ -381,7 +381,7 @@ void vdp_reset(void)
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}
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/* Mega Drive specific */
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else if ((system_hw == SYSTEM_MD) && (config.bios & 1) && !(system_bios & SYSTEM_MD))
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else if (((system_hw == SYSTEM_MD) || (system_hw == SYSTEM_MCD)) && (config.bios & 1) && !(system_bios & SYSTEM_MD))
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{
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/* force registers initialization (only if TMSS model is emulated and BOOT ROM is not loaded) */
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vdp_reg_w(0 , 0x04, 0);
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@ -479,8 +479,8 @@ int vdp_context_load(uint8 *state)
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load_param(&cached_write, sizeof(cached_write));
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/* restore FIFO timings */
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fifo_latency = 214 - (reg[12] & 1) * 24;
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fifo_latency <<= ((code & 0x0F) == 0x01);
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fifo_latency = (reg[12] & 1) ? 190 : 214;
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fifo_latency <<= ((code & 0x0F) < 0x03);
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/* restore current NTSC/PAL mode */
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if (system_hw & SYSTEM_MD)
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@ -567,8 +567,9 @@ void vdp_dma_update(unsigned int cycles)
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if (status & 8)
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{
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/* Process DMA until the end of VBLANK */
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/* NOTE: This is not 100% accurate since rate should be recalculated if */
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/* display width is changed during VBLANK but no games actually do this */
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/* NOTE: DMA timings can not change during VBLANK because active display width cannot be modified. */
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/* Indeed, writing VDP registers during DMA is either impossible (when doing DMA from 68k bus, CPU */
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/* is locked) or will abort DMA operation (in case of DMA Fill or Copy). */
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dma_cycles = (lines_per_frame * MCYCLES_PER_LINE) - cycles;
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}
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else
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@ -777,9 +778,11 @@ void vdp_68k_ctrl_w(unsigned int data)
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Each VRAM access is byte wide, so one VRAM write (word) need twice cycles.
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Note: Invalid code 0x02 (register write) apparently behaves the same as VRAM
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access, although no data is written in this case (fixes Clue menu)
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*/
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fifo_latency = 214 - (reg[12] & 1) * 24;
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fifo_latency <<= ((code & 0x0F) == 0x01);
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fifo_latency = (reg[12] & 1) ? 190 : 214;
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fifo_latency <<= ((code & 0x0F) < 0x03);
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}
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/* Mega Drive VDP control port specific (MS compatibility mode) */
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@ -1998,7 +2001,7 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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}
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/* Adjust FIFO timings for VRAM writes */
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fifo_latency <<= ((code & 0x0F) == 0x01);
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fifo_latency <<= ((code & 0x0F) < 0x03);
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/* Active display width modified during HBLANK (Bugs Bunny Double Trouble) */
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if ((v_counter < bitmap.viewport.h) && (cycles <= (mcycles_vdp + 860)))
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