[Core/VDP] improved DMA fill timing accuracy (again)

core/vdp_ctrl.c

@@ -593,7 +593,7 @@ int vdp_context_load(uint8 *state)
 
 void vdp_dma_update(unsigned int cycles)
 {
-  unsigned int dma_cycles, dma_bytes;
+  int dma_cycles, dma_bytes;
 
   /* DMA transfer rate (bytes per line) 
 
@@ -630,6 +630,12 @@ void vdp_dma_update(unsigned int cycles)
     else if (rate == 204) rate = 198; /* 6 refresh slots per line in H40 mode when display is off */
   }
 
+  /* Adjust DMA start cycle for DMA fill to take in account intial data port write */
+  else if (dmafill)
+  {
+    cycles += (2 * (MCYCLES_PER_LINE / rate));
+  }
+
   /* Available DMA cycles */
   if (status & 8)
   {
@@ -692,7 +698,7 @@ void vdp_dma_update(unsigned int cycles)
   }
 
   /* Process DMA */
-  if (dma_bytes)
+  if (dma_bytes > 0)
   {
     /* Update DMA length */
     dma_length -= dma_bytes;
@@ -2452,9 +2458,6 @@ static void vdp_68k_data_w_m5(unsigned int data)
   /* Check if DMA Fill is pending */
   if (dmafill)
   {
-    /* Clear DMA Fill pending flag */
-    dmafill = 0;
-
     /* DMA length */
     dma_length = (reg[20] << 8) | reg[19];
 
@@ -2466,6 +2469,9 @@ static void vdp_68k_data_w_m5(unsigned int data)
 
     /* Trigger DMA */
     vdp_dma_update(m68k.cycles);
+
+    /* Clear DMA Fill pending flag */
+    dmafill = 0;
   }
 }