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[Core/VDP] improved DMA fill timing accuracy (again)

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ekeeke 2024-03-02 08:42:03 +01:00
parent 5af254cd23
commit 8c72ba0d45
4 changed files with 11 additions and 5 deletions
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16
core/vdp_ctrl.c
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@ -593,7 +593,7 @@ int vdp_context_load(uint8 *state)
void vdp_dma_update(unsigned int cycles) void vdp_dma_update(unsigned int cycles)
{ {
unsigned int dma_cycles, dma_bytes; int dma_cycles, dma_bytes;
/* DMA transfer rate (bytes per line) /* DMA transfer rate (bytes per line)
@ -630,6 +630,12 @@ void vdp_dma_update(unsigned int cycles)
else if (rate == 204) rate = 198; /* 6 refresh slots per line in H40 mode when display is off */ else if (rate == 204) rate = 198; /* 6 refresh slots per line in H40 mode when display is off */
} }
/* Adjust DMA start cycle for DMA fill to take in account intial data port write */
else if (dmafill)
{
cycles += (2 * (MCYCLES_PER_LINE / rate));
}
/* Available DMA cycles */ /* Available DMA cycles */
if (status & 8) if (status & 8)
{ {
@ -692,7 +698,7 @@ void vdp_dma_update(unsigned int cycles)
} }
/* Process DMA */ /* Process DMA */
if (dma_bytes) if (dma_bytes > 0)
{ {
/* Update DMA length */ /* Update DMA length */
dma_length -= dma_bytes; dma_length -= dma_bytes;
@ -2452,9 +2458,6 @@ static void vdp_68k_data_w_m5(unsigned int data)
/* Check if DMA Fill is pending */ /* Check if DMA Fill is pending */
if (dmafill) if (dmafill)
{ {
/* Clear DMA Fill pending flag */
dmafill = 0;
/* DMA length */ /* DMA length */
dma_length = (reg[20] << 8) | reg[19]; dma_length = (reg[20] << 8) | reg[19];
@ -2466,6 +2469,9 @@ static void vdp_68k_data_w_m5(unsigned int data)
/* Trigger DMA */ /* Trigger DMA */
vdp_dma_update(m68k.cycles); vdp_dma_update(m68k.cycles);
/* Clear DMA Fill pending flag */
dmafill = 0;
} }
} }