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Making the core fully thread-safe

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This commit is contained in:
SergioMartin86 2024-04-01 06:57:30 +02:00
parent c02cf1cba3
commit 96e5c37a9b
4 changed files with 332 additions and 336 deletions
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3
core/cart_hw/sram.h
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@ -57,6 +57,3 @@ extern unsigned int sram_read_byte(unsigned int address);
extern unsigned int sram_read_word(unsigned int address);
extern void sram_write_byte(unsigned int address, unsigned int data);
extern void sram_write_word(unsigned int address, unsigned int data);
/* global variables */
extern T_SRAM sram;

1
core/m68k/s68kcpu.c
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@ -200,7 +200,6 @@ void s68k_set_fc_callback(void (*callback)(unsigned int new_fc))
#endif
extern void error(char *format, ...);
extern uint16_t v_counter;
/* update IRQ level according to triggered interrupts */
void s68k_update_irq(unsigned int mask)

332
core/state.c
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@ -7,299 +7,299 @@
// cart_hw/svp/svp16.h
ssp1601_t *ssp = NULL;
unsigned short *PC;
int g_cycles;
__thread ssp1601_t *ssp = NULL;
__thread unsigned short *PC;
__thread int g_cycles;
// cart_hw/areplay.c
struct action_replay_t action_replay;
__thread struct action_replay_t action_replay;
// cart_hw/eeprom_93c.c
T_EEPROM_93C eeprom_93c;
__thread T_EEPROM_93C eeprom_93c;
// cart_hw/eeprom_i2c.c
struct eeprom_i2c_t eeprom_i2c;
__thread struct eeprom_i2c_t eeprom_i2c;
// cart_hw/eeprom_spi.c
T_EEPROM_SPI spi_eeprom;
__thread T_EEPROM_SPI spi_eeprom;
// cart_hw/ggenie.c
struct ggenie_t ggenie;
__thread struct ggenie_t ggenie;
// cart_hw/megasd.c
T_MEGASD_HW megasd_hw;
__thread T_MEGASD_HW megasd_hw;
// cart_hw/sram.c
T_SRAM sram;
__thread T_SRAM sram;
// cd_hw/cdc.h
void (*dma_w)(unsigned int length); /* active DMA callback */
void (*halted_dma_w)(unsigned int length); /* halted DMA callback */
__thread void (*dma_w)(unsigned int length); /* active DMA callback */
__thread void (*halted_dma_w)(unsigned int length); /* halted DMA callback */
// cd_hw/cdd.c
#if defined(USE_LIBCHDR)
chd_file *libCHDRfile;
__thread chd_file *libCHDRfile;
#endif
cdStream *cdTrackStreams[100];
cdStream *cdTocStream;
__thread cdStream *cdTrackStreams[100];
__thread cdStream *cdTocStream;
// input_hw/activator.c
struct activator_t activator[2];
__thread struct activator_t activator[2];
// input_hw/gamepad.c
struct gamepad_t gamepad[MAX_DEVICES];
struct flipflop_t flipflop[2];
uint8_t latch;
__thread struct gamepad_t gamepad[MAX_DEVICES];
__thread struct flipflop_t flipflop[2];
__thread uint8_t latch;
// input_hw/graphic_board.c
struct graphic_board_t board;
__thread struct graphic_board_t board;
// input_hw/input.c
t_input input;
int old_system[2] = {-1,-1};
__thread t_input input;
__thread int old_system[2] = {-1,-1};
// input_hw/lightgun.c
struct lightgun_t lightgun;
__thread struct lightgun_t lightgun;
// input_hw/mouse.c
struct mouse_t mouse;
__thread struct mouse_t mouse;
// input_hw/paddle.c
struct paddle_t paddle[2];
__thread struct paddle_t paddle[2];
// input_hw/sportspad.c
struct sportspad_t sportspad[2];
__thread struct sportspad_t sportspad[2];
// input_hw/teamplayer.c
struct teamplayer_t teamplayer[2];
__thread struct teamplayer_t teamplayer[2];
// input_hw/terebi_oekaki.c
struct tablet_t tablet;
__thread struct tablet_t tablet;
// input_hw/xe_1ap.c
struct xe_1ap_t xe_1ap[2];
__thread struct xe_1ap_t xe_1ap[2];
// m68k/m68k.c
m68ki_cpu_core m68k;
m68ki_cpu_core s68k;
__thread m68ki_cpu_core m68k;
__thread m68ki_cpu_core s68k;
// m68k/m68kcpu.c
int m68k_irq_latency;
__thread int m68k_irq_latency;
// m68k/s68kcpu.c
int s68k_irq_latency;
__thread int s68k_irq_latency;
// sound/psg.c
struct psg_t psg;
__thread struct psg_t psg;
// sound/sound.c
#if defined(HAVE_YM3438_CORE) || defined(HAVE_OPLL_CORE)
int fm_buffer[1080 * 2 * 24]; // FM output buffer (large enough to hold a whole frame at original chips rate)
__thread int fm_buffer[1080 * 2 * 24]; // FM output buffer (large enough to hold a whole frame at original chips rate)
#else
int fm_buffer[1080 * 2];
__thread int fm_buffer[1080 * 2];
#endif
int fm_last[2];
int *fm_ptr;
int fm_cycles_ratio; // Cycle-accurate FM samples
int fm_cycles_start;
int fm_cycles_count;
int fm_cycles_busy;
__thread int fm_last[2];
__thread int *fm_ptr;
__thread int fm_cycles_ratio; // Cycle-accurate FM samples
__thread int fm_cycles_start;
__thread int fm_cycles_count;
__thread int fm_cycles_busy;
#ifdef HAVE_YM3438_CORE
ym3438_t ym3438;
short ym3438_accm[24][2];
int ym3438_sample[2];
int ym3438_cycles;
__thread ym3438_t ym3438;
__thread short ym3438_accm[24][2];
__thread int ym3438_sample[2];
__thread int ym3438_cycles;
#endif
#ifdef HAVE_OPLL_CORE
opll_t opll;
int opll_accm[18][2];
int opll_sample;
int opll_cycles;
int opll_status;
__thread opll_t opll;
__thread int opll_accm[18][2];
__thread int opll_sample;
__thread int opll_cycles;
__thread int opll_status;
#endif
// sound/ym2413.h
signed int output[2];
uint32_t LFO_AM;
int32_t LFO_PM;
YM2413 ym2413; /* emulated chip */
__thread signed int output[2];
__thread uint32_t LFO_AM;
__thread int32_t LFO_PM;
__thread YM2413 ym2413; /* emulated chip */
// sound/ym2612.c
YM2612 ym2612; /* emulated chip */
int32_t m2,c1,c2; /* current chip state - Phase Modulation input for operators 2,3,4 */
int32_t mem; /* one sample delay memory */
int32_t out_fm[6]; /* outputs of working channels */
uint32_t op_mask[8][4]; /* operator output bitmasking (DAC quantization) */
int chip_type = YM2612_DISCRETE; /* chip type */
__thread YM2612 ym2612; /* emulated chip */
__thread int32_t m2,c1,c2; /* current chip state - Phase Modulation input for operators 2,3,4 */
__thread int32_t mem; /* one sample delay memory */
__thread int32_t out_fm[6]; /* outputs of working channels */
__thread uint32_t op_mask[8][4]; /* operator output bitmasking (DAC quantization) */
__thread int chip_type = YM2612_DISCRETE; /* chip type */
// z80/z80.c
Z80_Regs Z80;
uint8_t z80_last_fetch;
unsigned char *z80_readmap[64];
unsigned char *z80_writemap[64];
uint32_t EA;
uint8_t SZ[256]; /* zero and sign flags */
uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
uint8_t SZP[256]; /* zero, sign and parity flags */
uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
uint8_t SZHVC_add[2*256*256]; /* flags for ADD opcode */
uint8_t SZHVC_sub[2*256*256]; /* flags for SUB opcode */
__thread Z80_Regs Z80;
__thread uint8_t z80_last_fetch;
__thread unsigned char *z80_readmap[64];
__thread unsigned char *z80_writemap[64];
__thread uint32_t EA;
__thread uint8_t SZ[256]; /* zero and sign flags */
__thread uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
__thread uint8_t SZP[256]; /* zero, sign and parity flags */
__thread uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
__thread uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
__thread uint8_t SZHVC_add[2*256*256]; /* flags for ADD opcode */
__thread uint8_t SZHVC_sub[2*256*256]; /* flags for SUB opcode */
#ifdef Z80_OVERCLOCK_SHIFT
uint32_t z80_cycle_ratio;
__thread uint32_t z80_cycle_ratio;
#endif
// genesis.c
// Cartdrigde / CD information
#ifdef USE_DYNAMIC_ALLOC
external_t *ext;
__thread external_t *ext;
#else
external_t ext;
__thread external_t ext;
#endif
uint8_t boot_rom[0x800];
uint8_t work_ram[0x10000];
uint8_t zram[0x2000];
uint32_t zbank;
uint8_t zstate;
uint8_t pico_current;
uint8_t tmss[4]; // TMSS security register
__thread uint8_t boot_rom[0x800];
__thread uint8_t work_ram[0x10000];
__thread uint8_t zram[0x2000];
__thread uint32_t zbank;
__thread uint8_t zstate;
__thread uint8_t pico_current;
__thread uint8_t tmss[4]; // TMSS security register
// io_ctrl.c
uint8_t io_reg[0x10];
uint8_t region_code = REGION_USA;
struct port_t port[3];
__thread uint8_t io_reg[0x10];
__thread uint8_t region_code = REGION_USA;
__thread struct port_t port[3];
// load_rom.c
ROMINFO rominfo;
uint8_t romtype;
uint8_t rom_region;
__thread ROMINFO rominfo;
__thread uint8_t romtype;
__thread uint8_t rom_region;
// membnk.c
t_zbank_memory_map zbank_memory_map[256];
__thread t_zbank_memory_map zbank_memory_map[256];
// system.c
t_bitmap bitmap;
t_snd snd;
uint32_t mcycles_vdp;
uint8_t system_hw;
uint8_t system_bios;
uint32_t system_clock;
int16_t SVP_cycles = 800;
uint8_t pause_b;
EQSTATE eq[2];
int16_t llp,rrp;
__thread t_bitmap bitmap;
__thread t_snd snd;
__thread uint32_t mcycles_vdp;
__thread uint8_t system_hw;
__thread uint8_t system_bios;
__thread uint32_t system_clock;
__thread int16_t SVP_cycles = 800;
__thread uint8_t pause_b;
__thread EQSTATE eq[2];
__thread int16_t llp,rrp;
// vdp.c
uint8_t ALIGNED_(4) sat[0x400]; /* Internal copy of sprite attribute table */
uint8_t ALIGNED_(4) vram[0x10000]; /* Video RAM (64K x 8-bit) */
uint8_t ALIGNED_(4) cram[0x80]; /* On-chip color RAM (64 x 9-bit) */
uint8_t ALIGNED_(4) vsram[0x80]; /* On-chip vertical scroll RAM (40 x 11-bit) */
uint8_t reg[0x20]; /* Internal VDP registers (23 x 8-bit) */
uint8_t hint_pending; /* 0= Line interrupt is pending */
uint8_t vint_pending; /* 1= Frame interrupt is pending */
uint16_t status; /* VDP status flags */
uint32_t dma_length; /* DMA remaining length */
uint32_t dma_endCycles; /* DMA end cycle */
uint8_t dma_type; /* DMA mode */
uint16_t ntab; /* Name table A base address */
uint16_t ntbb; /* Name table B base address */
uint16_t ntwb; /* Name table W base address */
uint16_t satb; /* Sprite attribute table base address */
uint16_t hscb; /* Horizontal scroll table base address */
uint8_t bg_name_dirty[0x800]; /* 1= This pattern is dirty */
uint16_t bg_name_list[0x800]; /* List of modified pattern indices */
uint16_t bg_list_index; /* # of modified patterns in list */
uint8_t hscroll_mask; /* Horizontal Scrolling line mask */
uint8_t playfield_shift; /* Width of planes A, B (in bits) */
uint8_t playfield_col_mask; /* Playfield column mask */
uint16_t playfield_row_mask; /* Playfield row mask */
uint16_t vscroll; /* Latched vertical scroll value */
uint8_t odd_frame; /* 1: odd field, 0: even field */
uint8_t im2_flag; /* 1= Interlace mode 2 is being used */
uint8_t interlaced; /* 1: Interlaced mode 1 or 2 */
uint8_t vdp_pal; /* 1: PAL , 0: NTSC (default) */
uint8_t h_counter; /* Horizontal counter */
uint16_t v_counter; /* Vertical counter */
uint16_t vc_max; /* Vertical counter overflow value */
uint16_t lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
uint16_t max_sprite_pixels; /* Max. sprites pixels per line (parsing & rendering) */
uint32_t fifo_cycles[4]; /* VDP FIFO read-out cycles */
uint32_t hvc_latch; /* latched HV counter */
uint32_t vint_cycle; /* VINT occurence cycle */
const uint8_t *hctab; /* pointer to H Counter table */
__thread uint8_t ALIGNED_(4) sat[0x400]; /* Internal copy of sprite attribute table */
__thread uint8_t ALIGNED_(4) vram[0x10000]; /* Video RAM (64K x 8-bit) */
__thread uint8_t ALIGNED_(4) cram[0x80]; /* On-chip color RAM (64 x 9-bit) */
__thread uint8_t ALIGNED_(4) vsram[0x80]; /* On-chip vertical scroll RAM (40 x 11-bit) */
__thread uint8_t reg[0x20]; /* Internal VDP registers (23 x 8-bit) */
__thread uint8_t hint_pending; /* 0= Line interrupt is pending */
__thread uint8_t vint_pending; /* 1= Frame interrupt is pending */
__thread uint16_t status; /* VDP status flags */
__thread uint32_t dma_length; /* DMA remaining length */
__thread uint32_t dma_endCycles; /* DMA end cycle */
__thread uint8_t dma_type; /* DMA mode */
__thread uint16_t ntab; /* Name table A base address */
__thread uint16_t ntbb; /* Name table B base address */
__thread uint16_t ntwb; /* Name table W base address */
__thread uint16_t satb; /* Sprite attribute table base address */
__thread uint16_t hscb; /* Horizontal scroll table base address */
__thread uint8_t bg_name_dirty[0x800]; /* 1= This pattern is dirty */
__thread uint16_t bg_name_list[0x800]; /* List of modified pattern indices */
__thread uint16_t bg_list_index; /* # of modified patterns in list */
__thread uint8_t hscroll_mask; /* Horizontal Scrolling line mask */
__thread uint8_t playfield_shift; /* Width of planes A, B (in bits) */
__thread uint8_t playfield_col_mask; /* Playfield column mask */
__thread uint16_t playfield_row_mask; /* Playfield row mask */
__thread uint16_t vscroll; /* Latched vertical scroll value */
__thread uint8_t odd_frame; /* 1: odd field, 0: even field */
__thread uint8_t im2_flag; /* 1= Interlace mode 2 is being used */
__thread uint8_t interlaced; /* 1: Interlaced mode 1 or 2 */
__thread uint8_t vdp_pal; /* 1: PAL , 0: NTSC (default) */
__thread uint8_t h_counter; /* Horizontal counter */
__thread uint16_t v_counter; /* Vertical counter */
__thread uint16_t vc_max; /* Vertical counter overflow value */
__thread uint16_t lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
__thread uint16_t max_sprite_pixels; /* Max. sprites pixels per line (parsing & rendering) */
__thread uint32_t fifo_cycles[4]; /* VDP FIFO read-out cycles */
__thread uint32_t hvc_latch; /* latched HV counter */
__thread uint32_t vint_cycle; /* VINT occurence cycle */
__thread const uint8_t *hctab; /* pointer to H Counter table */
uint8_t border; /* Border color index */
uint8_t pending; /* Pending write flag */
uint8_t code; /* Code register */
uint16_t addr; /* Address register */
uint16_t addr_latch; /* Latched A15, A14 of address */
uint16_t sat_base_mask; /* Base bits of SAT */
uint16_t sat_addr_mask; /* Index bits of SAT */
uint16_t dma_src; /* DMA source address */
int dmafill; /* DMA Fill pending flag */
int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
uint16_t fifo[4]; /* FIFO ring-buffer */
int fifo_idx; /* FIFO write index */
int fifo_byte_access; /* FIFO byte access flag */
int *fifo_timing; /* FIFO slots timing table */
int hblank_start_cycle; /* HBLANK flag set cycle */
int hblank_end_cycle; /* HBLANK flag clear cycle */
__thread uint8_t border; /* Border color index */
__thread uint8_t pending; /* Pending write flag */
__thread uint8_t code; /* Code register */
__thread uint16_t addr; /* Address register */
__thread uint16_t addr_latch; /* Latched A15, A14 of address */
__thread uint16_t sat_base_mask; /* Base bits of SAT */
__thread uint16_t sat_addr_mask; /* Index bits of SAT */
__thread uint16_t dma_src; /* DMA source address */
__thread int dmafill; /* DMA Fill pending flag */
__thread int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
__thread uint16_t fifo[4]; /* FIFO ring-buffer */
__thread int fifo_idx; /* FIFO write index */
__thread int fifo_byte_access; /* FIFO byte access flag */
__thread int *fifo_timing; /* FIFO slots timing table */
__thread int hblank_start_cycle; /* HBLANK flag set cycle */
__thread int hblank_end_cycle; /* HBLANK flag clear cycle */
// vdp_render.c
struct clip_t clip[2];
uint8_t ALIGNED_(4) bg_pattern_cache[0x80000]; /* Cached and flipped patterns */
uint8_t name_lut[0x400]; /* Sprite pattern name offset look-up table (Mode 5) */
uint32_t bp_lut[0x10000]; /* Bitplane to packed pixel look-up table (Mode 4) */
uint8_t lut[LUT_MAX][LUT_SIZE]; /* Layer priority pixel look-up tables */
PIXEL_OUT_T pixel[0x100]; /* Output pixel data look-up tables*/
PIXEL_OUT_T pixel_lut[3][0x200];
PIXEL_OUT_T pixel_lut_m4[0x40];
uint8_t linebuf[2][0x200]; /* Background & Sprite line buffers */
uint8_t spr_ovr; /* Sprite limit flag */
object_info_t obj_info[2][MAX_SPRITES_PER_LINE];
uint8_t object_count[2]; /* Sprite Counter */
uint16_t spr_col; /* Sprite Collision Info */
__thread struct clip_t clip[2];
__thread uint8_t ALIGNED_(4) bg_pattern_cache[0x80000]; /* Cached and flipped patterns */
__thread uint8_t name_lut[0x400]; /* Sprite pattern name offset look-up table (Mode 5) */
__thread uint32_t bp_lut[0x10000]; /* Bitplane to packed pixel look-up table (Mode 4) */
__thread uint8_t lut[LUT_MAX][LUT_SIZE]; /* Layer priority pixel look-up tables */
__thread PIXEL_OUT_T pixel[0x100]; /* Output pixel data look-up tables*/
__thread PIXEL_OUT_T pixel_lut[3][0x200];
__thread PIXEL_OUT_T pixel_lut_m4[0x40];
__thread uint8_t linebuf[2][0x200]; /* Background & Sprite line buffers */
__thread uint8_t spr_ovr; /* Sprite limit flag */
__thread object_info_t obj_info[2][MAX_SPRITES_PER_LINE];
__thread uint8_t object_count[2]; /* Sprite Counter */
__thread uint16_t spr_col; /* Sprite Collision Info */
size_t saveState(uint8_t* buffer)

332
core/state.h
View File

@ -55,297 +55,297 @@ extern void loadState(const uint8_t* buffer);
// cart_hw/svp/svp16.h
extern ssp1601_t *ssp;
extern unsigned short *PC;
extern int g_cycles;
extern __thread ssp1601_t *ssp;
extern __thread unsigned short *PC;
extern __thread int g_cycles;
// cart_hw/areplay.h
extern struct action_replay_t action_replay;
extern __thread struct action_replay_t action_replay;
// cart_hw/eeprom_93c.h
extern T_EEPROM_93C eeprom_93c;
extern __thread T_EEPROM_93C eeprom_93c;
// cart_hw/eeprom_i2c.h
extern struct eeprom_i2c_t eeprom_i2c;
extern __thread struct eeprom_i2c_t eeprom_i2c;
// cart_hw/eeprom_spi.h
extern T_EEPROM_SPI spi_eeprom;
extern __thread T_EEPROM_SPI spi_eeprom;
// cart_hw/ggenie.h
extern struct ggenie_t ggenie;
extern __thread struct ggenie_t ggenie;
// cart_hw/megasd.h
extern T_MEGASD_HW megasd_hw;
extern __thread T_MEGASD_HW megasd_hw;
// cart_hw/sram.h
extern T_SRAM sram;
extern __thread T_SRAM sram;
// cd_hw/cdc.h
extern void (*dma_w)(unsigned int length); /* active DMA callback */
extern void (*halted_dma_w)(unsigned int length); /* halted DMA callback */
extern __thread void (*dma_w)(unsigned int length); /* active DMA callback */
extern __thread void (*halted_dma_w)(unsigned int length); /* halted DMA callback */
// cd_hw/cdd.h
#if defined(USE_LIBCHDR)
extern chd_file *libCHDRfile;
extern __thread chd_file *libCHDRfile;
#endif
extern cdStream *cdTrackStreams[100];
extern cdStream *cdTocStream;
extern __thread cdStream *cdTrackStreams[100];
extern __thread cdStream *cdTocStream;
// input_hw/activator.h
extern struct activator_t activator[2];
extern __thread struct activator_t activator[2];
// input_hw/gamepad.h
extern struct gamepad_t gamepad[MAX_DEVICES];
extern struct flipflop_t flipflop[2];
extern uint8_t latch;
extern __thread struct gamepad_t gamepad[MAX_DEVICES];
extern __thread struct flipflop_t flipflop[2];
extern __thread uint8_t latch;
// input_hw/graphic_board.h
extern struct graphic_board_t board;
extern __thread struct graphic_board_t board;
// input_hw/input.h
extern t_input input;
extern int old_system[2];
extern __thread t_input input;
extern __thread int old_system[2];
// input_hw/lightgun.h
extern struct lightgun_t lightgun;
extern __thread struct lightgun_t lightgun;
// input_hw/mouse.h
extern struct mouse_t mouse;
extern __thread struct mouse_t mouse;
// input_hw/paddle.h
extern struct paddle_t paddle[2];
extern __thread struct paddle_t paddle[2];
// input_hw/sportspad.h
extern struct sportspad_t sportspad[2];
extern __thread struct sportspad_t sportspad[2];
// input_hw/teamplayer.h
extern struct teamplayer_t teamplayer[2];
extern __thread struct teamplayer_t teamplayer[2];
// input_hw/terebi_oekaki.h
extern struct tablet_t tablet;
extern __thread struct tablet_t tablet;
// input_hw/xe_1ap.c
extern struct xe_1ap_t xe_1ap[2];
extern __thread struct xe_1ap_t xe_1ap[2];
// m68k/m68k.h
extern m68ki_cpu_core m68k;
extern m68ki_cpu_core s68k;
extern __thread m68ki_cpu_core m68k;
extern __thread m68ki_cpu_core s68k;
// m68k/m68kcpu.c
extern int m68k_irq_latency;
extern __thread int m68k_irq_latency;
// m68k/s68kcpu.c
extern int s68k_irq_latency;
extern __thread int s68k_irq_latency;
// sound/psg.h
extern struct psg_t psg;
extern __thread struct psg_t psg;
// sound/sound.h
#if defined(HAVE_YM3438_CORE) || defined(HAVE_OPLL_CORE)
extern int fm_buffer[1080 * 2 * 24]; // FM output buffer (large enough to hold a whole frame at original chips rate)
extern __thread int fm_buffer[1080 * 2 * 24]; // FM output buffer (large enough to hold a whole frame at original chips rate)
#else
extern int fm_buffer[1080 * 2];
extern __thread int fm_buffer[1080 * 2];
#endif
extern int fm_last[2];
extern int *fm_ptr;
extern int fm_cycles_ratio; // Cycle-accurate FM samples
extern int fm_cycles_start;
extern int fm_cycles_count;
extern int fm_cycles_busy;
extern __thread int fm_last[2];
extern __thread int *fm_ptr;
extern __thread int fm_cycles_ratio; // Cycle-accurate FM samples
extern __thread int fm_cycles_start;
extern __thread int fm_cycles_count;
extern __thread int fm_cycles_busy;
#ifdef HAVE_YM3438_CORE
extern ym3438_t ym3438;
extern short ym3438_accm[24][2];
extern int ym3438_sample[2];
extern int ym3438_cycles;
extern __thread ym3438_t ym3438;
extern __thread short ym3438_accm[24][2];
extern __thread int ym3438_sample[2];
extern __thread int ym3438_cycles;
#endif
#ifdef HAVE_OPLL_CORE
extern opll_t opll;
extern int opll_accm[18][2];
extern int opll_sample;
extern int opll_cycles;
extern int opll_status;
extern __thread opll_t opll;
extern __thread int opll_accm[18][2];
extern __thread int opll_sample;
extern __thread int opll_cycles;
extern __thread int opll_status;
#endif
// sound/ym2413.h
extern signed int output[2];
extern uint32_t LFO_AM;
extern int32_t LFO_PM;
extern YM2413 ym2413; /* emulated chip */
extern __thread signed int output[2];
extern __thread uint32_t LFO_AM;
extern __thread int32_t LFO_PM;
extern __thread YM2413 ym2413; /* emulated chip */
// sound/ym2612.h
extern YM2612 ym2612; /* emulated chip */
extern int32_t m2,c1,c2; /* current chip state - Phase Modulation input for operators 2,3,4 */
extern int32_t mem; /* one sample delay memory */
extern int32_t out_fm[6]; /* outputs of working channels */
extern uint32_t op_mask[8][4]; /* operator output bitmasking (DAC quantization) */
extern int chip_type; /* chip type */
extern __thread YM2612 ym2612; /* emulated chip */
extern __thread int32_t m2,c1,c2; /* current chip state - Phase Modulation input for operators 2,3,4 */
extern __thread int32_t mem; /* one sample delay memory */
extern __thread int32_t out_fm[6]; /* outputs of working channels */
extern __thread uint32_t op_mask[8][4]; /* operator output bitmasking (DAC quantization) */
extern __thread int chip_type; /* chip type */
// z80/z80.h
extern Z80_Regs Z80;
extern uint8_t z80_last_fetch;
extern unsigned char *z80_readmap[64];
extern unsigned char *z80_writemap[64];
extern uint32_t EA;
extern uint8_t SZ[256]; /* zero and sign flags */
extern uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
extern uint8_t SZP[256]; /* zero, sign and parity flags */
extern uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
extern uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
extern uint8_t SZHVC_add[2*256*256]; /* flags for ADD opcode */
extern uint8_t SZHVC_sub[2*256*256]; /* flags for SUB opcode */
extern __thread Z80_Regs Z80;
extern __thread uint8_t z80_last_fetch;
extern __thread unsigned char *z80_readmap[64];
extern __thread unsigned char *z80_writemap[64];
extern __thread uint32_t EA;
extern __thread uint8_t SZ[256]; /* zero and sign flags */
extern __thread uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
extern __thread uint8_t SZP[256]; /* zero, sign and parity flags */
extern __thread uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
extern __thread uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
extern __thread uint8_t SZHVC_add[2*256*256]; /* flags for ADD opcode */
extern __thread uint8_t SZHVC_sub[2*256*256]; /* flags for SUB opcode */
#ifdef Z80_OVERCLOCK_SHIFT
extern uint32_t z80_cycle_ratio;
extern __thread uint32_t z80_cycle_ratio;
#endif
// genesis.h
// Cartdrigde / CD information
#ifdef USE_DYNAMIC_ALLOC
extern external_t *ext;
extern __thread external_t *ext;
#else
extern external_t ext;
extern __thread external_t ext;
#endif
extern uint8_t boot_rom[0x800];
extern uint8_t work_ram[0x10000];
extern uint8_t zram[0x2000];
extern uint32_t zbank;
extern uint8_t zstate;
extern uint8_t pico_current;
extern uint8_t tmss[4]; // TMSS security register
extern __thread uint8_t boot_rom[0x800];
extern __thread uint8_t work_ram[0x10000];
extern __thread uint8_t zram[0x2000];
extern __thread uint32_t zbank;
extern __thread uint8_t zstate;
extern __thread uint8_t pico_current;
extern __thread uint8_t tmss[4]; // TMSS security register
// io_ctrl.h
extern uint8_t io_reg[0x10];
extern uint8_t region_code;
extern struct port_t port[3];
extern __thread uint8_t io_reg[0x10];
extern __thread uint8_t region_code;
extern __thread struct port_t port[3];
// load_rom.h
extern ROMINFO rominfo;
extern uint8_t romtype;
extern uint8_t rom_region;
extern __thread ROMINFO rominfo;
extern __thread uint8_t romtype;
extern __thread uint8_t rom_region;
// membnk.h
extern t_zbank_memory_map zbank_memory_map[256];
extern __thread t_zbank_memory_map zbank_memory_map[256];
// system.h
extern t_bitmap bitmap;
extern t_snd snd;
extern uint32_t mcycles_vdp;
extern uint8_t system_hw;
extern uint8_t system_bios;
extern uint32_t system_clock;
extern int16_t SVP_cycles;
extern uint8_t pause_b;
extern EQSTATE eq[2];
extern int16_t llp,rrp;
extern __thread t_bitmap bitmap;
extern __thread t_snd snd;
extern __thread uint32_t mcycles_vdp;
extern __thread uint8_t system_hw;
extern __thread uint8_t system_bios;
extern __thread uint32_t system_clock;
extern __thread int16_t SVP_cycles;
extern __thread uint8_t pause_b;
extern __thread EQSTATE eq[2];
extern __thread int16_t llp,rrp;
// vdp.h
extern uint8_t ALIGNED_(4) sat[0x400]; /* Internal copy of sprite attribute table */
extern uint8_t ALIGNED_(4) vram[0x10000]; /* Video RAM (64K x 8-bit) */
extern uint8_t ALIGNED_(4) cram[0x80]; /* On-chip color RAM (64 x 9-bit) */
extern uint8_t ALIGNED_(4) vsram[0x80]; /* On-chip vertical scroll RAM (40 x 11-bit) */
extern uint8_t reg[0x20]; /* Internal VDP registers (23 x 8-bit) */
extern uint8_t hint_pending; /* 0= Line interrupt is pending */
extern uint8_t vint_pending; /* 1= Frame interrupt is pending */
extern uint16_t status; /* VDP status flags */
extern uint32_t dma_length; /* DMA remaining length */
extern uint32_t dma_endCycles; /* DMA end cycle */
extern uint8_t dma_type; /* DMA mode */
extern uint16_t ntab; /* Name table A base address */
extern uint16_t ntbb; /* Name table B base address */
extern uint16_t ntwb; /* Name table W base address */
extern uint16_t satb; /* Sprite attribute table base address */
extern uint16_t hscb; /* Horizontal scroll table base address */
extern uint8_t bg_name_dirty[0x800]; /* 1= This pattern is dirty */
extern uint16_t bg_name_list[0x800]; /* List of modified pattern indices */
extern uint16_t bg_list_index; /* # of modified patterns in list */
extern uint8_t hscroll_mask; /* Horizontal Scrolling line mask */
extern uint8_t playfield_shift; /* Width of planes A, B (in bits) */
extern uint8_t playfield_col_mask; /* Playfield column mask */
extern uint16_t playfield_row_mask; /* Playfield row mask */
extern uint16_t vscroll; /* Latched vertical scroll value */
extern uint8_t odd_frame; /* 1: odd field, 0: even field */
extern uint8_t im2_flag; /* 1= Interlace mode 2 is being used */
extern uint8_t interlaced; /* 1: Interlaced mode 1 or 2 */
extern uint8_t vdp_pal; /* 1: PAL , 0: NTSC (default) */
extern uint8_t h_counter; /* Horizontal counter */
extern uint16_t v_counter; /* Vertical counter */
extern uint16_t vc_max; /* Vertical counter overflow value */
extern uint16_t lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
extern uint16_t max_sprite_pixels; /* Max. sprites pixels per line (parsing & rendering) */
extern uint32_t fifo_cycles[4]; /* VDP FIFO read-out cycles */
extern uint32_t hvc_latch; /* latched HV counter */
extern uint32_t vint_cycle; /* VINT occurence cycle */
extern const uint8_t *hctab; /* pointer to H Counter table */
extern __thread uint8_t ALIGNED_(4) sat[0x400]; /* Internal copy of sprite attribute table */
extern __thread uint8_t ALIGNED_(4) vram[0x10000]; /* Video RAM (64K x 8-bit) */
extern __thread uint8_t ALIGNED_(4) cram[0x80]; /* On-chip color RAM (64 x 9-bit) */
extern __thread uint8_t ALIGNED_(4) vsram[0x80]; /* On-chip vertical scroll RAM (40 x 11-bit) */
extern __thread uint8_t reg[0x20]; /* Internal VDP registers (23 x 8-bit) */
extern __thread uint8_t hint_pending; /* 0= Line interrupt is pending */
extern __thread uint8_t vint_pending; /* 1= Frame interrupt is pending */
extern __thread uint16_t status; /* VDP status flags */
extern __thread uint32_t dma_length; /* DMA remaining length */
extern __thread uint32_t dma_endCycles; /* DMA end cycle */
extern __thread uint8_t dma_type; /* DMA mode */
extern __thread uint16_t ntab; /* Name table A base address */
extern __thread uint16_t ntbb; /* Name table B base address */
extern __thread uint16_t ntwb; /* Name table W base address */
extern __thread uint16_t satb; /* Sprite attribute table base address */
extern __thread uint16_t hscb; /* Horizontal scroll table base address */
extern __thread uint8_t bg_name_dirty[0x800]; /* 1= This pattern is dirty */
extern __thread uint16_t bg_name_list[0x800]; /* List of modified pattern indices */
extern __thread uint16_t bg_list_index; /* # of modified patterns in list */
extern __thread uint8_t hscroll_mask; /* Horizontal Scrolling line mask */
extern __thread uint8_t playfield_shift; /* Width of planes A, B (in bits) */
extern __thread uint8_t playfield_col_mask; /* Playfield column mask */
extern __thread uint16_t playfield_row_mask; /* Playfield row mask */
extern __thread uint16_t vscroll; /* Latched vertical scroll value */
extern __thread uint8_t odd_frame; /* 1: odd field, 0: even field */
extern __thread uint8_t im2_flag; /* 1= Interlace mode 2 is being used */
extern __thread uint8_t interlaced; /* 1: Interlaced mode 1 or 2 */
extern __thread uint8_t vdp_pal; /* 1: PAL , 0: NTSC (default) */
extern __thread uint8_t h_counter; /* Horizontal counter */
extern __thread uint16_t v_counter; /* Vertical counter */
extern __thread uint16_t vc_max; /* Vertical counter overflow value */
extern __thread uint16_t lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
extern __thread uint16_t max_sprite_pixels; /* Max. sprites pixels per line (parsing & rendering) */
extern __thread uint32_t fifo_cycles[4]; /* VDP FIFO read-out cycles */
extern __thread uint32_t hvc_latch; /* latched HV counter */
extern __thread uint32_t vint_cycle; /* VINT occurence cycle */
extern __thread const uint8_t *hctab; /* pointer to H Counter table */
extern uint8_t border; /* Border color index */
extern uint8_t pending; /* Pending write flag */
extern uint8_t code; /* Code register */
extern uint16_t addr; /* Address register */
extern uint16_t addr_latch; /* Latched A15, A14 of address */
extern uint16_t sat_base_mask; /* Base bits of SAT */
extern uint16_t sat_addr_mask; /* Index bits of SAT */
extern uint16_t dma_src; /* DMA source address */
extern int dmafill; /* DMA Fill pending flag */
extern int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
extern uint16_t fifo[4]; /* FIFO ring-buffer */
extern int fifo_idx; /* FIFO write index */
extern int fifo_byte_access; /* FIFO byte access flag */
extern int *fifo_timing; /* FIFO slots timing table */
extern int hblank_start_cycle; /* HBLANK flag set cycle */
extern int hblank_end_cycle; /* HBLANK flag clear cycle */
extern __thread uint8_t border; /* Border color index */
extern __thread uint8_t pending; /* Pending write flag */
extern __thread uint8_t code; /* Code register */
extern __thread uint16_t addr; /* Address register */
extern __thread uint16_t addr_latch; /* Latched A15, A14 of address */
extern __thread uint16_t sat_base_mask; /* Base bits of SAT */
extern __thread uint16_t sat_addr_mask; /* Index bits of SAT */
extern __thread uint16_t dma_src; /* DMA source address */
extern __thread int dmafill; /* DMA Fill pending flag */
extern __thread int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
extern __thread uint16_t fifo[4]; /* FIFO ring-buffer */
extern __thread int fifo_idx; /* FIFO write index */
extern __thread int fifo_byte_access; /* FIFO byte access flag */
extern __thread int *fifo_timing; /* FIFO slots timing table */
extern __thread int hblank_start_cycle; /* HBLANK flag set cycle */
extern __thread int hblank_end_cycle; /* HBLANK flag clear cycle */
// vdp_render.h
extern struct clip_t clip[2];
extern uint8_t ALIGNED_(4) bg_pattern_cache[0x80000]; /* Cached and flipped patterns */
extern uint8_t name_lut[0x400]; /* Sprite pattern name offset look-up table (Mode 5) */
extern uint32_t bp_lut[0x10000]; /* Bitplane to packed pixel look-up table (Mode 4) */
extern uint8_t lut[LUT_MAX][LUT_SIZE]; /* Layer priority pixel look-up tables */
extern PIXEL_OUT_T pixel[0x100]; /* Output pixel data look-up tables*/
extern PIXEL_OUT_T pixel_lut[3][0x200];
extern PIXEL_OUT_T pixel_lut_m4[0x40];
extern uint8_t linebuf[2][0x200]; /* Background & Sprite line buffers */
extern uint8_t spr_ovr; /* Sprite limit flag */
extern object_info_t obj_info[2][MAX_SPRITES_PER_LINE];
extern uint8_t object_count[2]; /* Sprite Counter */
extern uint16_t spr_col; /* Sprite Collision Info */
extern __thread struct clip_t clip[2];
extern __thread uint8_t ALIGNED_(4) bg_pattern_cache[0x80000]; /* Cached and flipped patterns */
extern __thread uint8_t name_lut[0x400]; /* Sprite pattern name offset look-up table (Mode 5) */
extern __thread uint32_t bp_lut[0x10000]; /* Bitplane to packed pixel look-up table (Mode 4) */
extern __thread uint8_t lut[LUT_MAX][LUT_SIZE]; /* Layer priority pixel look-up tables */
extern __thread PIXEL_OUT_T pixel[0x100]; /* Output pixel data look-up tables*/
extern __thread PIXEL_OUT_T pixel_lut[3][0x200];
extern __thread PIXEL_OUT_T pixel_lut_m4[0x40];
extern __thread uint8_t linebuf[2][0x200]; /* Background & Sprite line buffers */
extern __thread uint8_t spr_ovr; /* Sprite limit flag */
extern __thread object_info_t obj_info[2][MAX_SPRITES_PER_LINE];
extern __thread uint8_t object_count[2]; /* Sprite Counter */
extern __thread uint16_t spr_col; /* Sprite Collision Info */