[Core/VDP] improved accuracy of DMA to CRAM/VSRAM (verified on real hardware by Mask of Destiny) and DMA Fill timings

This commit is contained in:
ekeeke 2024-02-23 14:48:00 +01:00
parent 5f2f0ce89f
commit 9a0a1c2922
4 changed files with 10 additions and 0 deletions

Binary file not shown.

Binary file not shown.

Before

Width:  |  Height:  |  Size: 3.8 MiB

After

Width:  |  Height:  |  Size: 3.8 MiB

Binary file not shown.

Before

Width:  |  Height:  |  Size: 4.0 MiB

After

Width:  |  Height:  |  Size: 4.0 MiB

View File

@ -623,6 +623,13 @@ void vdp_dma_update(unsigned int cycles)
/* Adjust for 68k bus DMA to VRAM (one word = 2 access) or DMA Copy (one read + one write = 2 access) */ /* Adjust for 68k bus DMA to VRAM (one word = 2 access) or DMA Copy (one read + one write = 2 access) */
rate = rate >> (dma_type & 1); rate = rate >> (dma_type & 1);
/* Adjust for 68k bus DMA to CRAM or VSRAM when display is off (one additional access slot is lost for each refresh slot) */
if (dma_type == 0)
{
if (rate == 166) rate = 161; /* 5 refresh slots per line in H32 mode when display is off */
else if (rate == 204) rate = 198; /* 6 refresh slots per line in H40 mode when display is off */
}
/* Remaining DMA cycles */ /* Remaining DMA cycles */
if (status & 8) if (status & 8)
{ {
@ -2444,6 +2451,9 @@ static void vdp_68k_data_w_m5(unsigned int data)
dma_length = 0x10000; dma_length = 0x10000;
} }
/* Take into account initial data word processing */
dma_length += 2;
/* Trigger DMA */ /* Trigger DMA */
vdp_dma_update(m68k.cycles); vdp_dma_update(m68k.cycles);
} }