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[Core/VDP] improved accuracy of DMA to CRAM/VSRAM (verified on real hardware by Mask of Destiny) and DMA Fill timings
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@ -623,6 +623,13 @@ void vdp_dma_update(unsigned int cycles)
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/* Adjust for 68k bus DMA to VRAM (one word = 2 access) or DMA Copy (one read + one write = 2 access) */
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/* Adjust for 68k bus DMA to VRAM (one word = 2 access) or DMA Copy (one read + one write = 2 access) */
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rate = rate >> (dma_type & 1);
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rate = rate >> (dma_type & 1);
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/* Adjust for 68k bus DMA to CRAM or VSRAM when display is off (one additional access slot is lost for each refresh slot) */
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if (dma_type == 0)
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{
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if (rate == 166) rate = 161; /* 5 refresh slots per line in H32 mode when display is off */
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else if (rate == 204) rate = 198; /* 6 refresh slots per line in H40 mode when display is off */
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}
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/* Remaining DMA cycles */
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/* Remaining DMA cycles */
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if (status & 8)
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if (status & 8)
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{
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{
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@ -2444,6 +2451,9 @@ static void vdp_68k_data_w_m5(unsigned int data)
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dma_length = 0x10000;
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dma_length = 0x10000;
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}
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}
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/* Take into account initial data word processing */
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dma_length += 2;
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/* Trigger DMA */
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/* Trigger DMA */
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vdp_dma_update(m68k.cycles);
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vdp_dma_update(m68k.cycles);
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}
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}
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