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[Core/VDP] added some precision in comments about delay on invalid VRAM writes
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@ -805,11 +805,17 @@ void vdp_68k_ctrl_w(unsigned int data)
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/*
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FIFO emulation (Chaos Engine/Soldier of Fortune, Double Clutch, Sol Deace)
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--------------------------------------------------------------------------
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Each VRAM access is byte wide, so one VRAM write (word) need twice cycles.
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Each VRAM access is byte wide, so one VRAM write (word) need two slot access.
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Note: Invalid code 0x02 (register write) apparently behaves the same as VRAM
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access, although no data is written in this case (fixes Clue menu)
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*/
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NOTE: Invalid code 0x02 (register write) should not behave the same as VRAM
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access, i.e data is ignored and only one access slot is used for each word,
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BUT a few games ("Clue", "Microcosm") which accidentally corrupt code value
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will have issues when emulating FIFO timings. They likely work fine on real
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hardware because of periodical 68k wait-states which have been observed and
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would naturaly add some delay between writes. Until those wait-states are
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accurately measured and emulated, delay is forced when invalid code value
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is being used.
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*/
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fifo_byte_access = ((code & 0x0F) <= 0x02);
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}
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@ -2303,7 +2309,7 @@ static void vdp_bus_w(unsigned int data)
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default:
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{
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/* add some delay until 68k periodical wait-states (RAM refresh ?) are accurately emulated (needed by "Clue" & "Microcosm") */
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/* add some delay until 68k periodical wait-states are accurately emulated ("Clue", "Microcosm") */
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m68k.cycles += 2;
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#ifdef LOGERROR
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error("[%d(%d)][%d(%d)] Invalid (%d) 0x%x write -> 0x%x (%x)\n", v_counter, m68k.cycles/MCYCLES_PER_LINE-1, m68k.cycles, m68k.cycles%MCYCLES_PER_LINE, code, addr, data, m68k_get_reg(M68K_REG_PC));
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