mirror of
https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-04 01:45:08 +01:00
[Core/VDP] improved FIFO timings accuracy (fixes "Overdrive" Demo)
This commit is contained in:
EkeEke
twinaphex
parent
f4014c3ef1
commit
adae91bd65
@ -357,7 +357,7 @@ void system_frame_gen(int do_skip)
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/* reset VDP FIFO */
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fifo_write_cnt = 0;
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fifo_lastwrite = 0;
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fifo_slots = 0;
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/* update 6-Buttons & Lightguns */
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input_refresh();
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@ -703,7 +703,7 @@ void system_frame_scd(int do_skip)
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/* reset VDP FIFO */
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fifo_write_cnt = 0;
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fifo_lastwrite = 0;
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fifo_slots = 0;
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/* update 6-Buttons & Lightguns */
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input_refresh();
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@ -1032,7 +1032,7 @@ void system_frame_sms(int do_skip)
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/* reset VDP FIFO */
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fifo_write_cnt = 0;
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fifo_lastwrite = 0;
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fifo_slots = 0;
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/* update 6-Buttons & Lightguns */
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input_refresh();
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133
core/vdp_ctrl.c
133
core/vdp_ctrl.c
@ -85,8 +85,8 @@ uint8 vdp_pal; /* 1: PAL , 0: NTSC (default) */
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uint16 v_counter; /* Vertical counter */
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uint16 vc_max; /* Vertical counter overflow value */
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uint16 lines_per_frame; /* PAL: 313 lines, NTSC: 262 lines */
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int32 fifo_write_cnt; /* VDP writes fifo count */
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uint32 fifo_lastwrite; /* last VDP write cycle */
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int32 fifo_write_cnt; /* VDP FIFO write count */
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uint32 fifo_slots; /* VDP FIFO access slot count */
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uint32 hvc_latch; /* latched HV counter */
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const uint8 *hctab; /* pointer to H Counter table */
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@ -134,9 +134,10 @@ static uint16 sat_addr_mask; /* Index bits of SAT */
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static uint16 dma_src; /* DMA source address */
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static uint16 dmafill; /* DMA Fill setup */
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static uint32 dma_endCycles; /* 68k cycles to DMA end */
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static uint32 fifo_latency; /* CPU access latency */
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static int cached_write; /* 2nd part of 32-bit CTRL port write (Genesis mode) or LSB of CRAM data (Game Gear mode) */
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static uint16 fifo[4]; /* FIFO buffer */
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static int fifo_byte_access; /* FIFO byte access flag */
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static uint32 fifo_cycles; /* FIFO next access cycle */
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/* set Z80 or 68k interrupt lines */
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static void (*set_irq_line)(unsigned int level);
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@ -227,8 +228,10 @@ void vdp_reset(void)
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im2_flag = 0;
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interlaced = 0;
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fifo_write_cnt = 0;
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fifo_lastwrite = 0;
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fifo_cycles = 0;
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fifo_slots = 0;
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cached_write = -1;
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fifo_byte_access = 1;
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ntab = 0;
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ntbb = 0;
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@ -259,9 +262,6 @@ void vdp_reset(void)
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/* default Window clipping */
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window_clip(0,0);
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/* default FIFO timings */
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fifo_latency = 214;
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/* reset VDP status (FIFO empty flag is set) */
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if (system_hw & SYSTEM_MD)
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{
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@ -478,9 +478,8 @@ int vdp_context_load(uint8 *state)
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load_param(&cached_write, sizeof(cached_write));
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/* restore FIFO timings */
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fifo_latency = (reg[12] & 1) ? 190 : 214;
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fifo_latency <<= ((code & 0x0F) < 0x03);
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/* restore FIFO byte access flag */
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fifo_byte_access = ((code & 0x0F) < 0x03);
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/* restore current NTSC/PAL mode */
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if (system_hw & SYSTEM_MD)
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@ -769,20 +768,12 @@ void vdp_68k_ctrl_w(unsigned int data)
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/*
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FIFO emulation (Chaos Engine/Soldier of Fortune, Double Clutch, Sol Deace)
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--------------------------------------------------------------------------
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CPU access per line is limited during active display:
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H32: 16 access --> 3420/16 = ~214 Mcycles between access
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H40: 18 access --> 3420/18 = ~190 Mcycles between access
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This is an approximation: on real hardware, access slots are fixed.
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Each VRAM access is byte wide, so one VRAM write (word) need twice cycles.
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Note: Invalid code 0x02 (register write) apparently behaves the same as VRAM
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access, although no data is written in this case (fixes Clue menu)
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*/
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fifo_latency = (reg[12] & 1) ? 190 : 214;
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fifo_latency <<= ((code & 0x0F) < 0x03);
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fifo_byte_access = ((code & 0x0F) <= 0x02);
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}
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/* Mega Drive VDP control port specific (MS compatibility mode) */
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@ -1221,8 +1212,11 @@ unsigned int vdp_68k_ctrl_r(unsigned int cycles)
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{
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unsigned int temp;
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/* Update FIFO flags */
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/* Update FIFO status flags if not empty */
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if (fifo_write_cnt)
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{
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vdp_fifo_update(cycles);
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}
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/* Update DMA Busy flag */
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if ((status & 2) && !dma_length && (cycles >= dma_endCycles))
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@ -1980,9 +1974,6 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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/* Update clipping */
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window_clip(reg[17], 1);
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/* Update fifo timings */
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fifo_latency = 190;
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}
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else
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{
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@ -1997,14 +1988,8 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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/* Update clipping */
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window_clip(reg[17], 0);
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/* Update FIFO timings */
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fifo_latency = 214;
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}
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/* Adjust FIFO timings for VRAM writes */
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fifo_latency <<= ((code & 0x0F) < 0x03);
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/* Active display width modified during HBLANK (Bugs Bunny Double Trouble) */
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if ((v_counter < bitmap.viewport.h) && (cycles <= (mcycles_vdp + 860)))
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{
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@ -2063,38 +2048,84 @@ static void vdp_reg_w(unsigned int r, unsigned int d, unsigned int cycles)
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}
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}
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/*--------------------------------------------------------------------------*/
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/* FIFO update function (Genesis mode only) */
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/* FIFO emulation (Mega Drive VDP specific) */
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/* ---------------------------------------- */
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/* */
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/* CPU access to VRAM, CRAM & VSRAM is limited during active display: */
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/* H32 mode -> 16 access per line */
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/* H40 mode -> 18 access per line */
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/* */
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/* with fixed access slots timings detailled below. */
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/* */
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/* Each VRAM access is byte wide, so one VRAM write (word) need two slots. */
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/* */
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/*--------------------------------------------------------------------------*/
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static void vdp_fifo_update(unsigned int cycles)
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{
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if (fifo_write_cnt > 0)
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{
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/* Get number of FIFO reads */
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int fifo_read = ((cycles - fifo_lastwrite) / fifo_latency);
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int slots, count = 0;
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if (fifo_read > 0)
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const int *fifo_timing;
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const int fifo_cycles_h32[16+2] =
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{
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/* Process FIFO entries */
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fifo_write_cnt -= fifo_read;
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230, 510, 810, 970, 1130, 1450, 1610, 1770, 2090, 2250, 2410, 2730, 2890, 3050, 3350, 3370,
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MCYCLES_PER_LINE + 230, MCYCLES_PER_LINE + 510
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};
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const int fifo_cycles_h40[18+2] =
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{
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352, 820, 948, 1076, 1332, 1460, 1588, 1844, 1972, 2100, 2356, 2484, 2612, 2868, 2996, 3124, 3364, 3380,
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MCYCLES_PER_LINE + 352, MCYCLES_PER_LINE + 820
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};
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/* number of access slots up to current line */
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if (reg[12] & 0x01)
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{
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fifo_timing = fifo_cycles_h40;
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slots = 18 * (cycles / MCYCLES_PER_LINE);
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}
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else
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{
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fifo_timing = fifo_cycles_h32;
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slots = 16 * (cycles / MCYCLES_PER_LINE);
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}
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/* number of access slots within current line */
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cycles = cycles % MCYCLES_PER_LINE;
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while (fifo_timing[count] <= cycles)
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{
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count++;
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}
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/* number of processed FIFO entries since last access */
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slots = (slots + count - fifo_slots) >> fifo_byte_access;
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if (slots > 0)
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{
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/* process FIFO entries */
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fifo_write_cnt -= slots;
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/* Clear FIFO full flag */
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status &= 0xFEFF;
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/* Check remaining FIFO entries */
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if (fifo_write_cnt <= 0)
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{
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/* No more FIFO entries */
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fifo_write_cnt = 0;
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/* Set FIFO empty flag */
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status |= 0x200;
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fifo_write_cnt = 0;
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}
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/* Update FIFO cycle count */
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fifo_lastwrite += (fifo_read * fifo_latency);
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}
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/* Update FIFO access slot counter */
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fifo_slots += (slots << fifo_byte_access);
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}
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/* next FIFO update cycle */
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fifo_cycles = mcycles_vdp + fifo_timing[count | fifo_byte_access];
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}
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@ -2252,9 +2283,11 @@ static void vdp_68k_data_w_m4(unsigned int data)
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}
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else
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{
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/* CPU is halted until last FIFO entry has been processed (Chaos Engine, Soldiers of Fortune, Double Clutch) */
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fifo_lastwrite += fifo_latency;
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m68k.cycles = fifo_lastwrite;
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/* CPU is halted until next FIFO entry processing */
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m68k.cycles = fifo_cycles;
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/* Update FIFO access slot counter */
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fifo_slots = fifo_slots + 1 + fifo_byte_access;
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}
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}
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@ -2342,9 +2375,11 @@ static void vdp_68k_data_w_m5(unsigned int data)
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}
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else
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{
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/* CPU is halted until last FIFO entry has been processed (Chaos Engine, Soldiers of Fortune, Double Clutch) */
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fifo_lastwrite += fifo_latency;
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m68k.cycles = fifo_lastwrite;
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/* CPU is halted until next FIFO entry processing (Chaos Engine / Soldiers of Fortune, Double Clutch, Titan Overdrive Demo) */
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m68k.cycles = fifo_cycles;
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/* Update FIFO access slot counter */
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fifo_slots += (1 + fifo_byte_access);
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}
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}
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@ -75,7 +75,7 @@ extern uint16 vc_max;
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extern uint16 vscroll;
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extern uint16 lines_per_frame;
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extern int32 fifo_write_cnt;
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extern uint32 fifo_lastwrite;
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extern uint32 fifo_slots;
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extern uint32 hvc_latch;
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extern const uint8 *hctab;
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