The-Homebrew-Cloud/Genesis-Plus-GX
2
0
Fork 0
mirror of https://github.com/ekeeke/Genesis-Plus-GX.git synced 2024-11-13 06:15:07 +01:00
Code Issues Packages Projects Releases Wiki Activity

[Core/CD] fixed CD communication registers state on peripheral reset (fixes SUB-CPU side initialization in MSU-MD sample demo and some Mode 1 patched games using MSU-MD driver)

Browse Source
This commit is contained in:
ekeeke 2020-09-08 01:57:44 +02:00
parent 2ca416f738
commit c718b1f3f2
5 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
HISTORY.txt
View File

@ -45,6 +45,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
* fixed CDD seek command again (Final Fight CD freeze with model 2 BIOS)
* fixed CDD status reported during seek/access time (sound effect synchronization issue in Bari Arm)
* fixed word access to CDD control register (fixes spurious audio track playback on startup with Mode 1 patched games using MSU-MD driver)
* fixed CD communication registers state on peripheral reset (fixes SUB-CPU side initialization in MSU-MD sample demo and some Mode 1 patched games using MSU-MD driver)
* optimized Sub-CPU / Main-CPU synchronization
[Core/MD]

BIN
builds/genesis_plus_gx_libretro.dll
View File

Binary file not shown.

BIN
builds/genplus_cube.dol
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 3.7 MiB

After

Width:  |  Height:  |  Size: 3.7 MiB

BIN
builds/genplus_wii.dol
View File

Binary file not shown.
Side by Side Swipe Overlay

Before

Width:  |  Height:  |  Size: 3.9 MiB

After

Width:  |  Height:  |  Size: 3.9 MiB

8
core/cd_hw/scd.c
View File

@ -1564,7 +1564,6 @@ void scd_init(void)
void scd_reset(int hard)
{
/* TODO: figure what exactly is resetted when RESET bit is cleared by SUB-CPU */
if (hard)
{
/* Clear all ASIC registers by default */
@ -1612,8 +1611,11 @@ void scd_reset(int hard)
}
else
{
/* Clear only SUB-CPU side registers */
memset(&scd.regs[0x04>>1], 0, sizeof(scd.regs) - 4);
/* TODO: figure what exactly is reset when RESET bit is cleared by SUB-CPU */
/* Clear only SUB-CPU side registers (communication registers are not cleared, see msu-md-sample.bin) */
scd.regs[0x04>>1].w = 0x0000;
scd.regs[0x0c>>1].w = 0x0000;
memset(&scd.regs[0x30>>1], 0, sizeof(scd.regs) - 0x30);
}
/* SUB-CPU side default values */