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[Core/CD] fixed CD communication registers state on peripheral reset (fixes SUB-CPU side initialization in MSU-MD sample demo and some Mode 1 patched games using MSU-MD driver)

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ekeeke 2020-09-08 01:57:44 +02:00
parent 2ca416f738
commit c718b1f3f2
5 changed files with 6 additions and 3 deletions
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1
HISTORY.txt
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@ -45,6 +45,7 @@ Genesis Plus GX 1.7.5 (xx/xx/xxxx) (Eke-Eke)
* fixed CDD seek command again (Final Fight CD freeze with model 2 BIOS) * fixed CDD seek command again (Final Fight CD freeze with model 2 BIOS)
* fixed CDD status reported during seek/access time (sound effect synchronization issue in Bari Arm) * fixed CDD status reported during seek/access time (sound effect synchronization issue in Bari Arm)
* fixed word access to CDD control register (fixes spurious audio track playback on startup with Mode 1 patched games using MSU-MD driver) * fixed word access to CDD control register (fixes spurious audio track playback on startup with Mode 1 patched games using MSU-MD driver)
* fixed CD communication registers state on peripheral reset (fixes SUB-CPU side initialization in MSU-MD sample demo and some Mode 1 patched games using MSU-MD driver)
* optimized Sub-CPU / Main-CPU synchronization * optimized Sub-CPU / Main-CPU synchronization
[Core/MD] [Core/MD]

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builds/genesis_plus_gx_libretro.dll
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builds/genplus_cube.dol
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8
core/cd_hw/scd.c
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@ -1564,7 +1564,6 @@ void scd_init(void)
void scd_reset(int hard) void scd_reset(int hard)
{ {
/* TODO: figure what exactly is resetted when RESET bit is cleared by SUB-CPU */
if (hard) if (hard)
{ {
/* Clear all ASIC registers by default */ /* Clear all ASIC registers by default */
@ -1612,8 +1611,11 @@ void scd_reset(int hard)
} }
else else
{ {
/* Clear only SUB-CPU side registers */ /* TODO: figure what exactly is reset when RESET bit is cleared by SUB-CPU */
memset(&scd.regs[0x04>>1], 0, sizeof(scd.regs) - 4); /* Clear only SUB-CPU side registers (communication registers are not cleared, see msu-md-sample.bin) */
scd.regs[0x04>>1].w = 0x0000;
scd.regs[0x0c>>1].w = 0x0000;
memset(&scd.regs[0x30>>1], 0, sizeof(scd.regs) - 0x30);
} }
/* SUB-CPU side default values */ /* SUB-CPU side default values */