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https://github.com/ekeeke/Genesis-Plus-GX.git
synced 2024-11-04 18:05:06 +01:00
finally fixed interlaced mode, reimplemented frame counters
This commit is contained in:
ekeeke31
parent
e822832b99
commit
c8d27f6740
@ -1,6 +1,9 @@
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Genesis Plus for Gamecube
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------------------------------
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[NGC/Wii]
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- fixed video issues in original interlaced modes
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- fixed some statibilty issues
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1.3.1 (20/12/2008):
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-------------------
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@ -1109,7 +1109,7 @@ void showrominfo ()
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* Main Menu
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*
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****************************************************************************/
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void MainMenu ()
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void MainMenu (u32 fps)
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{
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menu = 0;
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int ret;
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@ -1139,6 +1139,7 @@ void MainMenu ()
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{
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crccheck = crc32 (0, &sram.sram[0], 0x10000);
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if (genromsize && (crccheck != sram.crc)) strcpy (menutitle, "*** SRAM has been modified ***");
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else if (genromsize) sprintf (menutitle, "%d FPS",fps);
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ret = domenu (&items[0], count, 0);
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switch (ret)
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@ -130,6 +130,10 @@ int main (int argc, char *argv[])
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DI_Init();
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#endif
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uint32 RenderedFrames;
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uint32 TotalFrames;
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uint32 FramesPerSecond;
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/* initialize OGC subsystems */
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ogc_video__init();
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ogc_input__init();
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@ -192,11 +196,14 @@ int main (int argc, char *argv[])
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ogc_video__stop();
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/* go to menu */
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MainMenu ();
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MainMenu (FramesPerSecond);
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ConfigRequested = 0;
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/* reset frame sync */
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frameticker = 0;
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frameticker = 0;
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RenderedFrames = 0;
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TotalFrames = 0;
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FramesPerSecond = vdp_rate;
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/* start Audio & Video */
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ogc_audio__start();
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@ -223,9 +230,18 @@ int main (int argc, char *argv[])
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/* update video & audio */
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ogc_audio__update();
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ogc_video__update();
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RenderedFrames++;
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}
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frameticker--;
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TotalFrames++;
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if (TotalFrames == vdp_rate)
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{
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FramesPerSecond = RenderedFrames;
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RenderedFrames = 0;
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TotalFrames = 0;
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}
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}
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return 0;
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@ -534,11 +534,14 @@ static void gxReset(void)
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if (rmode->viTVMode & VI_NON_INTERLACE) VIDEO_WaitVSync();
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else while (VIDEO_GetNextField() != odd_frame) VIDEO_WaitVSync();
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/* resynchronize field & restore VSYNC handler */
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whichfb = odd_frame;
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VIDEO_SetPreRetraceCallback(xfb_swap);
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VIDEO_Flush();
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VIDEO_WaitVSync();
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/* resynchronize interlaced field */
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if (interlaced && !config.render)
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{
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whichfb = odd_frame;
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VIDEO_SetPreRetraceCallback(xfb_swap);
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VIDEO_Flush();
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VIDEO_WaitVSync();
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}
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}
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/* Set Menu Video mode */
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@ -560,8 +563,8 @@ void ogc_video__stop(void)
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void ogc_video__start()
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{
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/* clear screen */
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VIDEO_ClearFrameBuffer(vmode, xfb[whichfb], COLOR_BLACK);
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VIDEO_ClearFrameBuffer(vmode, xfb[whichfb], COLOR_BLACK);
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VIDEO_ClearFrameBuffer(vmode, xfb[0], COLOR_BLACK);
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VIDEO_ClearFrameBuffer(vmode, xfb[1], COLOR_BLACK);
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VIDEO_Flush();
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VIDEO_WaitVSync();
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@ -654,14 +657,29 @@ void ogc_video__update()
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draw_square ();
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GX_DrawDone ();
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/* special case: interlaced display */
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if (interlaced && !config.render && (odd_frame == whichfb))
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/* single-field interlaced display requires proper sync*/
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if (interlaced && !config.render)
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{
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/* resynchronize frame emulation */
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odd_frame = whichfb ^1;
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/* desync */
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if (odd_frame == whichfb)
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{
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/* force field resync */
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odd_frame = whichfb ^ 1;
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}
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else
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{
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/* copy EFB to proper XFB */
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GX_CopyDisp (xfb[whichfb], GX_TRUE);
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GX_Flush ();
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}
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}
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else
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{
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/* swap XFB */
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whichfb ^= 1;
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VIDEO_SetNextFramebuffer (xfb[whichfb]);
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VIDEO_Flush ();
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/* copy EFB to current XFB */
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GX_CopyDisp (xfb[whichfb], GX_TRUE);
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GX_Flush ();
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@ -30,7 +30,7 @@ extern void reloadrom();
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extern void ClearGGCodes();
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extern void GetGGEntries();
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extern void legal();
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extern void MainMenu();
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extern void MainMenu(u32 fps);
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extern void set_region();
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extern int ManageSRAM(u8 direction, u8 device);
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extern int ManageState(u8 direction, u8 device);
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@ -115,8 +115,8 @@
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#include "shared.h"
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/* globals */
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#define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
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#define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
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#define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
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#define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
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#define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
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#define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
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@ -586,8 +586,8 @@ typedef struct
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/***********************************************************/
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typedef struct
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{
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FM_CH CH[6]; /* channel state */
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UINT8 dacen; /* DAC mode */
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FM_CH CH[6]; /* channel state */
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UINT8 dacen; /* DAC mode */
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INT32 dacout; /* DAC output */
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FM_OPN OPN; /* OPN state */
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} YM2612;
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@ -599,7 +599,7 @@ static YM2612 ym2612;
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static INT32 m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
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static INT32 mem; /* one sample delay memory */
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static INT32 out_fm[8]; /* outputs of working channels */
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static UINT32 LFO_AM; /* runtime LFO calculations helper */
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static UINT32 LFO_AM; /* runtime LFO calculations helper */
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static INT32 LFO_PM; /* runtime LFO calculations helper */
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@ -922,20 +922,20 @@ INLINE void advance_eg_channel(FM_SLOT *SLOT)
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break;
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case EG_DEC: /* decay phase */
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if ( !(ym2612.OPN.eg_cnt & ((1<<SLOT->eg_sh_d1r)-1) ) )
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{
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if ( !(ym2612.OPN.eg_cnt & ((1<<SLOT->eg_sh_d1r)-1) ) )
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{
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if (SLOT->ssg&0x08) /* SSG EG type envelope selected */
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SLOT->volume += 6 * eg_inc[SLOT->eg_sel_d1r + ((ym2612.OPN.eg_cnt>>SLOT->eg_sh_d1r)&7)];
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else
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else
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SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((ym2612.OPN.eg_cnt>>SLOT->eg_sh_d1r)&7)];
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}
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/* check transition even if no volume update: this fixes the case when SL = MIN_ATT_INDEX */
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if ( SLOT->volume >= (INT32)(SLOT->sl) )
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{
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SLOT->volume = (INT32)(SLOT->sl);
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SLOT->state = EG_SUS;
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}
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if ( SLOT->volume >= (INT32)(SLOT->sl) )
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{
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SLOT->volume = (INT32)(SLOT->sl);
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SLOT->state = EG_SUS;
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}
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break;
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@ -991,8 +991,8 @@ INLINE void advance_eg_channel(FM_SLOT *SLOT)
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if ( SLOT->volume >= MAX_ATT_INDEX )
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SLOT->volume = MAX_ATT_INDEX;
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/* do not change SLOT->state (verified on real chip) */
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}
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}
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}
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break;
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case EG_REL: /* release phase */
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@ -1011,7 +1011,6 @@ INLINE void advance_eg_channel(FM_SLOT *SLOT)
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}
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}
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break;
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}
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unsigned int out = (UINT32)SLOT->volume;
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@ -1229,7 +1228,8 @@ INLINE void refresh_fc_eg_slot(FM_SLOT *SLOT , int fc , int kc )
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/* update phase increment counters */
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INLINE void refresh_fc_eg_chan(FM_CH *CH )
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{
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if( CH->SLOT[SLOT1].Incr==-1){
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if( CH->SLOT[SLOT1].Incr==-1)
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{
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int fc = CH->fc;
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int kc = CH->kcode;
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refresh_fc_eg_slot(&CH->SLOT[SLOT1] , fc , kc );
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@ -1380,20 +1380,20 @@ INLINE void CSMKeyControll(FM_CH *CH)
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if (!CH->SLOT[SLOT2].key)
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{
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FM_KEYON(CH,SLOT2);
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FM_KEYON(CH,SLOT2);
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FM_KEYOFF(CH,SLOT2);
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}
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if (!CH->SLOT[SLOT3].key)
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{
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FM_KEYON(CH,SLOT3);
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FM_KEYON(CH,SLOT3);
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FM_KEYOFF(CH,SLOT3);
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}
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if (!CH->SLOT[SLOT4].key)
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{
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FM_KEYON(CH,SLOT4);
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FM_KEYOFF(CH,SLOT4);
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FM_KEYON(CH,SLOT4);
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FM_KEYOFF(CH,SLOT4);
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}
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}
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@ -1662,8 +1662,8 @@ static void OPNWriteReg(int r, int v)
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CH->block_fnum = (blk<<11) | fn;
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CH->SLOT[SLOT1].Incr=-1;
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}
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break;
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}
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case 1: /* 0xa4-0xa6 : FNUM2,BLK */
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ym2612.OPN.ST.fn_h = v&0x3f;
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break;
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@ -1695,8 +1695,8 @@ static void OPNWriteReg(int r, int v)
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CH->ALGO = v&7;
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CH->FB = feedback ? feedback+6 : 0;
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setup_connection( CH, c );
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}
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break;
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}
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case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (ym2612/YM2610B/YM2610/YM2608) */
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/* b0-2 PMS */
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CH->pms = (v & 7) * 32; /* CH->pms = PM depth * 32 (index in lfo_pm_table) */
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@ -1707,7 +1707,6 @@ static void OPNWriteReg(int r, int v)
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/* PAN : b7 = L, b6 = R */
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ym2612.OPN.pan[ c*2 ] = (v & 0x80) ? ~0 : 0;
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ym2612.OPN.pan[ c*2+1 ] = (v & 0x40) ? ~0 : 0;
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break;
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}
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break;
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@ -130,7 +130,7 @@ int system_frame (int do_skip)
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/* parse sprites for line 0 (done on last line) */
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parse_satb (0x80);
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/* process frame */
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/* process scanlines */
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for (line = 0; line < lines_per_frame; line ++)
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{
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/* update VCounter */
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12
source/vdp.c
12
source/vdp.c
@ -1,4 +1,4 @@
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/***************************************************************************************
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/***************************************************************************************
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* Genesis Plus 1.2a
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* Video Display Processor (memory handlers)
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*
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@ -338,7 +338,7 @@ static inline void dma_copy(void)
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int source = (reg[22] << 8 | reg[21]) & 0xFFFF;
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if (!length) length = 0x10000;
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dma_type = 3;
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dma_type = 3;
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dma_length = length;
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dma_update();
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@ -623,7 +623,7 @@ static inline void vdp_reg_w(unsigned int r, unsigned int d)
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/* Check if Mode 4 (SMS mode) has been activated
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According to official doc, VDP registers #11 to #23 can not be written unless bit2 in register #1 is set
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Fix Captain Planet & Avengers (Alt version), Bass Master Classic Pro Edition (they incidentally activate Mode 4)
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*/
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*/
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if (!(reg[1] & 4) && (r > 10)) return;
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switch(r)
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@ -887,7 +887,7 @@ unsigned int vdp_data_r(void)
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}
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/* Increment address register */
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addr += reg[15];
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addr += reg[15];
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/* return data */
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return (temp);
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@ -898,7 +898,7 @@ unsigned int vdp_hvc_r(void)
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uint8 hc = (hc_latch & 0x100) ? (hc_latch & 0xFF) : hctab[count_m68k % m68cycles_per_line];
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uint8 vc = vctab[v_counter];
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/* interlace mode 2 */
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/* interlace mode 2 */
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if (im2_flag) vc = (vc << 1) | ((vc >> 7) & 1);
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return ((vc << 8) | hc);
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@ -908,7 +908,7 @@ unsigned int vdp_hvc_r(void)
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void vdp_test_w(unsigned int value)
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{
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#ifdef LOGERROR
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error("Unused VDP Write 0x%x (%08x)", value, m68k_get_reg (NULL, M68K_REG_PC));
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error("Unused VDP Write 0x%x (%08x)\n", value, m68k_get_reg (NULL, M68K_REG_PC));
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#endif
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}
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