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https://github.com/ekeeke/Genesis-Plus-GX.git
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[Z80] fixed state of CPU registers on reset: fixes missing sound in Defender/Defender 2 (Williams Arcade Classics)
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@ -41,6 +41,7 @@ of samples per frame and keeping PSG & FM chips in sync.
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* updated Z80 core to last version (fixes interrupt Mode 0 timing and some BIT instructions).
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* updated Z80 core to last version (fixes interrupt Mode 0 timing and some BIT instructions).
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* fixed some Z80 instructions timing.
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* fixed some Z80 instructions timing.
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* fixed state of Z80 registers on reset (sound issues with Defender & Defender 2 in Williams Arcade Classics)
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* improved Z80 interrupt accuracy
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* improved Z80 interrupt accuracy
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* improved 68k accuracy (initial Reset timing + auto-vectored interrupts handling).
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* improved 68k accuracy (initial Reset timing + auto-vectored interrupts handling).
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* improved 68k timing accuracy for DIVU/DVIS (thanks to Jorge Cwik) & MULU/MULS instructions.
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* improved 68k timing accuracy for DIVU/DVIS (thanks to Jorge Cwik) & MULU/MULS instructions.
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@ -3353,6 +3353,9 @@ void z80_init(const void *config, int (*irqcallback)(int))
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}
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}
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/* Reset registers to their initial values */
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/* Reset registers to their initial values */
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memset(&Z80, 0, sizeof(Z80));
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IX = IY = 0xffff; /* IX and IY are FFFF after a reset! */
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F = ZF; /* Zero flag is set */
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Z80.daisy = config;
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Z80.daisy = config;
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Z80.irq_callback = irqcallback;
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Z80.irq_callback = irqcallback;
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@ -3370,25 +3373,19 @@ void z80_init(const void *config, int (*irqcallback)(int))
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****************************************************************************/
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****************************************************************************/
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void z80_reset(void)
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void z80_reset(void)
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{
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{
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/* save previous values */
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void *config = (void *) Z80.daisy;
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int (*irqcallback)(int) = Z80.irq_callback;
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/* Reset registers to their initial values */
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memset(&Z80, 0, sizeof(Z80));
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Z80.daisy = config;
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Z80.irq_callback = irqcallback;
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IX = IY = 0xffff; /* IX and IY are FFFF after a reset! */
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F = ZF; /* Zero flag is set */
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PC = 0x0000;
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PC = 0x0000;
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I = 0;
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I = 0;
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R = 0;
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R = 0;
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R2 = 0;
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R2 = 0;
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IM = 0;
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IFF1 = IFF2 = 0;
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HALT = 0;
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Z80.nmi_state = CLEAR_LINE;
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Z80.nmi_state = CLEAR_LINE;
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Z80.nmi_pending = FALSE;
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Z80.nmi_pending = FALSE;
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Z80.irq_state = CLEAR_LINE;
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Z80.irq_state = CLEAR_LINE;
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Z80.after_ei = FALSE;
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Z80.after_ei = FALSE;
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WZ=PCD;
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WZ=PCD;
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}
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}
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